Toshiba TMPR4925, Manual

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Chapter 7 External Bus Controller
7-59
7.6
Flash ROM, SRAM Usage Example
Figure 7.6.1 illustrates example Flash ROM connections, and Figure 7.6.2 illustrates example SRAM
connections. Also, Figure 7.6.3 illustrates example connections with the SDRAM and the bus separated.
Since connecting multiple memory devices such as SDRAM and ROM onto a single bus increases the
load, 100 MHz class high-speed SDRAM access may not be performed normally. As a corrective measure,
there is a way of reducing the bus load by connecting a device other than SDRAM via a buffer. If such a
method is employed, directional control becomes necessary since the data becomes bidirectional.
The TX4925 prepares the BUSSPRT* signal for performing data directional control (see Figure 7.6.3).
BUSSPRT* is asserted when the External Bus Controller channel is active and a Read operation is being
performed.
Figure 7.6.1 Flash ROM (x16 Bits) Connection Example (32-bit Data Bus)
Figure 7.6.2 SRAM (x16 Bits) Connection Example (32-bit Data Bus)
ADDR[19:0]
UAE
CE * [0]
SWE *
OE *
DATA[31:0]
TX4925
ADDR[19:0]
A[19:0]
A20
CE *
WE *
OE *
D[15:0]
ADDR[12] (ADDR[20])
A[19:0]
A20
CE *
WE *
OE *
D[15:0]
Flash ROM (x16 bits)
D[31:16] D[15:0]
D[31:16]
BWE * [3:0]
ADDR[19:0]
CE
*
[1]
SWE *
OE *
DATA[31:0]
TX4925
ADDR[19:0]
UB LB
A[19:0]
CS *
WE *
OE
*
D[15:0]
SRAM (x16 Bits)
D[15:0]
UB LB
A[19:0]
CS *
WE *
OE
*
D[15:0]
BWE
*
[3] BWE
*
[2] BWE
*
[1] BWE
*
[0]