Toshiba TMPR4925, Manual

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Chapter 16 CHI Module
16-32
16.4.12 CHI Clock Register (CHICLOCK) 0xA828
31 16
Reserved
: Type
: Initial value
15 10 9 8 7 0
Reserved CDIR MCLK CDIV
R/W R/W R/W : Type
0 1 00000000 : Initial value
Bits Mnemonic Field Name Description
31:10
⎯
Reserved
⎯
9 CDIR CHICLKDIR CHICLKDIR bit (Initial value: 0, R/W)
This bit controls the direction of the CHICLK pin.
0: input (CHI slave mode)
1: output (CHI master mode)
Note: Please set the same value CHICLKDIR and CHIFSDIR. Each set the
difference value (CHIFSDIR = 1, CHICLKDIR = 0 or CHIFSDIR = 0,
CHICLKDIR = 1) can’t recommend
8 MCLK CHIMCLKEN CHIMCLKEN bit (Initial value: 1, R/W)
This bit is used to enable or disable the CHICLK counter and CHICLK clock
generation. This bit controls the direction of the CHICLK pin.
0: disable (halting the clock to the CHI Module in order to reduce power
consumption)
1: enable
7:0 CDIV[7:0] CHICLKDIV CHICLKDIV bit (Initial value: 0000_0000, R/W)
These bits define the divide-modulus for the programmable divider used to generate
CHICLK. The divide-modulus is equal to (CHI 2). (See the following Table
16.4.2.)
Note: CLKDIV less than 1 can’t recommend
Figure 16.4.12 CHI Clock Register (CHICLOCK)
Table 16.4.2 CHI Clock Divide
CHICLKDIV[7:0] Divide-modulus
2 4
: :
N
:
N+2
:
253 255
254 256