Toshiba TMPR4925, Manual

Page: 60 / 590

Chapter 3 Signals
3-2
3.1.2 SDRAM Interface Signals
Table 3.1.2 SDRAM Interface Signals
Signal Name Type Description Initial State
SDCLK[1:0] Output SDRAM Controller Clock
Clock signals used by SDRAM/SyncFlash. The clock frequency is the same as the G-
Bus clock (GBUSCLK) frequency.
When these clock signals are not used, the pins can be set to L using the SDCLK
Enable field of the pin configuration register (PCFG.SDCLKEN[1:0]).
All High
SDCLKIN Input/output SDRAM Feedback Clock input
Feedback clock signal for SDRAM controller input signals.
Input
CKE Output Clock Enable
CKE signal for SDRAM/SyncFlash.
High
SDCS[3:0]
*
Output Synchronous Memory Device Chip Select
Chip select signals for SDRAM/SyncFlash.
All High
RAS * Output Row Address Strobe
RAS signal for SDRAM/SyncFlash.
High
CAS * Output Column Address Strobe
CAS signal for SDRAM/SyncFlash.
High
WE * Output Write Enable
WR signal for SDRAM/SyncFlash.
High
DQM[3:0] Output Data Mask
During a write cycle, the DQM signals function as a data mask. During a read cycle,
they control the SDRAM output buffers. The bits correspond to the following data bus
signals:
DQM[3]:DATA[31:24], DQM[2]:DATA[23:16]
DQM[1]:DATA[15:8], DQM[0]:DATA[7:0]
All High
RP * Output This pin should be left open. Low