Toshiba TMPR4925, Manual

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Table of Contents
iv
9.5.2 Single Write (32-bit Bus) .................................................................................................................... 9-20
9.5.3 Burst Read (32-bit Bus)....................................................................................................................... 9-22
9.5.4 Burst Write (32-bit Bus) ...................................................................................................................... 9-23
9.5.5 Burst Write (32-bit Bus, Slow Write Burst) ........................................................................................ 9-24
9.5.6 Single Read (16-bit Bus) ..................................................................................................................... 9-25
9.5.7 Single Write (16-bit Bus) .................................................................................................................... 9-27
9.5.8 Low Power Consumption and Power Down Mode ............................................................................. 9-29
9.6 SDRAM Usage Example ............................................................................................................................. 9-33
10. PCI Controller....................................................................................................................................................... 10-1
10.1 Features ........................................................................................................................................................ 10-1
10.1.1 Overall................................................................................................................................................. 10-1
10.1.2 Initiator Function................................................................................................................................. 10-1
10.1.3 Target Function.................................................................................................................................... 10-1
10.1.4 PCI Arbiter .......................................................................................................................................... 10-2
10.1.5 PDMAC (PCI DMA Controller) ......................................................................................................... 10-2
10.2 Block Diagram ............................................................................................................................................. 10-3
10.3 Detailed Explanation.................................................................................................................................... 10-4
10.3.1 Terminology Explanation .................................................................................................................... 10-4
10.3.2 On-Chip Register................................................................................................................................. 10-4
10.3.3 Supported PCI Bus Commands ........................................................................................................... 10-6
10.3.4 Initiator Access (G-Bus
→
PCI Bus address conversion) ................................................................... 10-8
10.3.5 Target Access (PCI Bus
→
G-Bus Address Conversion) .................................................................. 10-10
10.3.6 Post Write Function ........................................................................................................................... 10-13
10.3.7 Endian Switching Function ............................................................................................................... 10-13
10.3.8 Power Management........................................................................................................................... 10-14
10.3.9 PDMAC (PCI DMA Controller) ....................................................................................................... 10-15
10.3.10 Error Detection, Interrupt Reporting ................................................................................................. 10-19
10.3.11 PCI Bus Arbiter ................................................................................................................................. 10-20
10.3.12 PCI Boot............................................................................................................................................ 10-22
10.3.13 Set Configuration Space.................................................................................................................... 10-23
10.3.14 PCI Clock Signal ............................................................................................................................... 10-23
10.4 PCI Controller Control Register................................................................................................................. 10-24
10.4.1 ID Register (PCIID) 0xD000 ............................................................................................................ 10-26
10.4.2 PCI Status, Command Register (PCISTATUS) 0xD004 ................................................................... 10-27
10.4.3 Class Code, Revision ID Register (PCICCREV) 0xD008 ................................................................ 10-29
10.4.4 PCI Configuration 1 Register (PCICFG1) 0xD00C .......................................................................... 10-30
10.4.5 P2G Memory Space 0 PCI Base Address Register (P2GM0PBASE) 0xD010 ................................. 10-31
10.4.6 P2G Memory Space 1 PCI Base Address Register (P2GM1PBASE) 0xD014 ................................. 10-32
10.4.7 P2G Memory Space 2 PCI Base Address Register (P2GM2PBASE) 0xD018 ................................. 10-33
10.4.8 P2G I/O Space PCI Base Address Register (P2GIOPBASE) 0xD01C ............................................. 10-34
10.4.9 Subsystem ID Register (PCISID) 0xD02C ....................................................................................... 10-35
10.4.10 Capabilities Pointer Register (PCICAPPTR) 0xD034 ...................................................................... 10-36
10.4.11 PCI Configuration 2 Register (PCICFG2) 0xD03C .......................................................................... 10-37
10.4.12 G2P Timeout Count Register (G2PTOCNT) 0xD040 ....................................................................... 10-38
10.4.13 G2P Configuration Register (G2PCFG) 0xD060 ............................................................................. 10-39
10.4.14 G2P Status Register (G2PSTATUS) 0xD064 .................................................................................... 10-41
10.4.15 G2P Interrupt Mask Register (G2PMASK) 0xD068......................................................................... 10-42
10.4.16 Satellite Mode PCI Status Register (PCISSTATUS) 0xD088 ........................................................... 10-43
10.4.17 PCI Status Interrupt Mask Register (PCIMASK) 0xD08C ............................................................... 10-44
10.4.18 P2G Configuration Register (P2GCFG) 0xD090 .............................................................................. 10-45
10.4.19 P2G Status Register (P2GSTATUS) 0xD094 .................................................................................... 10-46
10.4.20 P2G Interrupt Mask Register (P2GMASK) 0xD098......................................................................... 10-47
10.4.21 P2G Current Command Register (P2GCCMD) 0xD09C .................................................................. 10-48
10.4.22 PCI Bus Arbiter Request Port Register (PBAREQPORT) 0xD100 .................................................. 10-49
10.4.23 PCI Bus Arbiter Configuration Register (PBACFG) 0xD104........................................................... 10-51
10.4.24 PCI Bus Arbiter Status Register (PBASTATUS) 0xD108................................................................. 10-52
10.4.25 PCI Bus Arbiter Interrupt Mask Register (PBAMASK) 0xD10C ..................................................... 10-53
10.4.26 PCI Bus Arbiter Broken Master Register (PBABM) 0xD110 ........................................................... 10-54