Chapter 10 PCI Controller
10-41
10.4.14 G2P Status Register (G2PSTATUS)
0xD064
31
16
Reserved
:
Type
: Initial value
15 9 8 7 6 5 4 2 1 0
Reserved IOBFE IIBFE
MDFE MDPE
Reserved
IDTTOE IDRTOE
R
R
R/W1C R/W1C
R/W1C
R/W1C :
Type
1
1
0
0 0
0
:
Initial
value
Bits Mnemonic Field
Name
Description
31:9
⎯
Reserved
⎯
8 IOBFE
Initiator Out-
Bound FIFO
Empty
Initiator Out-Bound FIFO Empty (Initial value: 1, R)
1: Indicates that the Initiator Out-Bound FIFO is empty.
0: Indicates that the Initiator Out-Bound FIFO is not empty.
This is a diagnostic function.
7 IIBFE
Initiator In-Bound
FIFO Empty
Initiator In-Bound FIFO Empty (Initial value: 1, R)
1: Indicates that the Initiator In-Bound FIFO is empty.
0: Indicates that the Initiator In-Bound FIFO is not empty.
This is a diagnostic function.
6 MDFE
Master Direct
Fatal Error
Master Direct Fatal Error (Initial value: 0, R/W1C)
This bit is set when the initiator detects a fatal error in master direct cycle.
A fatal error is an event such as one of the following:
•
Master abort
•
Target abort
•
Trdy timeout
•
Retry timeout
The G2PSTATUS.MDFE bit is set if one of the above events occurs.
5 MDPE
Master Direct
Parity Error
Master Direct Parity Error (Initial value: 0, R/W1C)
This bit is set when the initiator detects a parity error in master direct cycle.
4:2
⎯
Reserved
⎯
1 IDTTOE
TRDY Timeout
Error
Initiator Detected TRDY Time Out Error (Initial value: 0, R/W1C)
This bit is set when the initiator detects a TRDY timeout.
0 IDRTOE
Retry Timeout
Error
Initiator Detected Retry Time Out Error (Initial value: 0, R/W1C)
This bit is set when the initiator detects a Retry timeout.
Figure 10.4.14 G2P Status Register
Summary of Contents for TMPR4925
Page 1: ...64 Bit TX System RISC TX49 Family TMPR4925 Rev 3 0 ...
Page 4: ......
Page 15: ...Handling Precautions ...
Page 16: ......
Page 18: ...1 Using Toshiba Semiconductors Safely 1 2 ...
Page 40: ...3 General Safety Precautions and Usage Considerations 3 18 ...
Page 42: ...4 Precautions and Usage Considerations 4 2 ...
Page 43: ...TMPR4925 ...
Page 44: ......
Page 54: ...Chapter 1 Features 1 8 ...
Page 58: ...Chapter 2 Block Diagram 2 4 ...
Page 88: ...Chapter 4 Address Mapping 4 12 ...
Page 226: ...Chapter 8 DMA Controller 8 58 ...
Page 260: ...Chapter 9 SDRAM Controller 9 34 ...
Page 480: ...Chapter 15 Interrupt Controller 15 32 ...
Page 554: ...Chapter 19 Real Time Clock RTC 19 8 ...
Page 555: ...Chapter 20 Removed 20 1 20 Removed ...
Page 556: ...Chapter 20 Removed 20 2 ...
Page 564: ...Chapter 21 Extended EJTAG Interface 21 8 ...
Page 580: ...Chapter 22 Electrical Characteristics 22 16 ...
Page 588: ...Chapter 24 Usage Notes 24 2 ...