Toshiba TMPR4925, Manual

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Chapter 19 Real Time Clock (RTC)
19-6
19.4.5 RTC Control Register (RTCCTRL) 0xF910
31 16
Reserved
: Type
: Initial value
15 8 7 6 5 4 3 2 1 0
Reserved
DISRTINT DISALINT
FRZPRE FRZRTC RTCCLR Reserved TSTCLK RTCTST
R/W R/W R/W R/W R/W R/W R/W : Type
1 1 0 0 0 0 0 : Initial value
Bits Mnemonic Field Name Explanation
31:8
⎯
Reserved
⎯
7 DISRTINT Disable RTC
Interrupt Disable RTC Interrupt (Initial value: 1, R/W)
Disable RTC Interrupt. If clear, the interrupt occurs when RTC counter reaches a
value of “0xffffffffff”.
1: Disable
0: Enable
6 DISALINT Disable Alarm
Interrupt Disable Alarm Interrupt (Initial value: 1, R/W)
Disable Alarm Interrupt. If clear, the interrupt occurs when RTC counter reaches a
value that is equal to the value of Alarm count.
1: Disable
0: Enable
5 FRZPRE Freeze Prescaler
Freeze Prescaler (Initial value: 0, R/W)
Setting this bit will cause the lower 8 bits of the RTC counter to freeze. This bit is a
test bit and customers can’t use it.
1: Freeze
0: Run
4 FRZRTC Freeze RTC Freeze RTC (Initial value: 0, R/W)
Setting this bit will cause the upper 36 bits of the RTC counter to freeze. This bit is
a test bit and customers can’t use it.
1: Freeze
0: Run
3 RTCCLR RTC Clear RTC Clear (Initial value: 0, R/W)
Setting this bit to a logic “1” will cause all 44 bits of the RTC counter to initialize to
“0x0000000_0000”. The RTC counter will stay cleared and the counter will not start
counting until this bit is cleared back to a logic “0”.
1: Stop
0: Run
2
⎯
Reserved
⎯
1 TSTCLK Enable Test
Clock
Enable Test Clock (Initial value: 0, R/W)
Setting this bit will cause the 32 kHz input clock for the RTC counter to be driven by
the IMBUSCLK instead of the 32 kHz input pin. This bit is a test bit and customers
can’t use it.
0: 32 KHz input
1: IMBUSCLK
0 RTCTST Enable RTC Test Enable RTC Test (Initial value: 0, R/W)
Setting this bit will cause all five of the 8-bit counters and the 4-bit counter that
comprise the RTC counter to count together. This bit is a test bit and customers
can’t use it.
0: Normal run
1: Test run
Figure 19.4.5 RTC Control Register (RTCCTRL)