Toshiba TMPR4925, Manual

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Chapter 23 Pin Layout, Package
23-2
A B C D E F G H J K
20 RAS * SDCS[0] * DQM[1] DQM[0] RP * DATA[15] DATA[29] DATA[28] DATA[27] DATA[26]
19 SDCS[1]
*
DQM[3] DQM[2] CAS
*
DATA[31] DATA[30] DATA[13] DATA[12] DATA[11] DATA[10]
18 ADDR[6] ADDR[5] VDDS WE
*
VDDS DATA[14] VDDC VDDS VDDC VDDC
17 ADDR[8] ADDR[7] Vss Vss Vss Vss Vss Vss Vss Vss
16 ADDR[10] ADDR[9] VDDC VDDS
15 ADDR[13] ADDR[12] ADDR[11] Vss
14 SADDR10 ADDR[14] VDDC Vss
13 ADDR[18] ADDR[19] ADDR[16] VDDS
12 SDCS[2] * CKE ADDR[17] Vss
11 SDCLK[0] SDCS[3] * SCANENB * VDDS
10 SDCLK[1] RESET * VDDC Vss
9 SDCLKIN PIO[20] TRST
*
PON
*
8 PIO[19] PIO[18] PIO[23] VDDS
7 PIO[22] PIO[21] VDDC Vss
6 PIO[27] PIO[29] PIO[28] PIO[30]
5 PIO[24] PIO[31] PIO[25] VDDC TOP View
4 PIO[26] TDO VDDC Vss REQ[2] * VDDS Vss VDDS Vss VDDS
3 TDI TCK VDDS GNT[1]
*
GNT[3]
*
PCIAD[30] VDDC PCIAD[25] ID_SEL PCIAD[21]
2 TMS GNT[0] * REQ[0] * REQ[1] * REQ[3] * PCIAD[29] PCIAD[27] PCIAD[24] PCIAD[23] PCIAD[20]
1 PCICLKIO PCICLK[1] PCICLK[2] GNT[2] * PCIAD[31] PCIAD[28] PCIAD[26] C_BE[3] PCIAD[22] PCIAD[19]
Table 23.1.1 Pin layout (1/2)