Renesas H8S/2100 Series, Hardware Manual

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Section 16 CIR Interface
Rev. 1.00 Apr. 28, 2008 Page 478 of 994
REJ09B0452-0100
16.3.6 Receive Data Register 0 to 17 (CIRRDR0 to CIRRDR17)
CIRRDR0 to CIRRDR17 are an 18-byte register that stores receive data, totaling to 18 bytes.
CIRRDR0 to CIRRDR17 share one byte of the register address. A receive data in CIRRDR should
be read after the CIR has finished data reception (CIRBUSY = 0). If CIRRDR is read during the
CIR reception (CIRBUSY = 1), an undefined value is read.
Bit Bit Name
Initial
Value R/W Description
7 to 0 CIRRDR7 to
CIRRDR0 H'00 R Stores the CIR receive data.
16.3.7 Header Minimum/Maximum High-Level Period Register (HHMIN and HHMAX)
HHMIN and HHMAX control the noise canceler circuit, and specify the minimum and maximum
high-level period for a header or repeat header, and low-level period for a stop.
•
HHMIN
Bit Bit Name
Initial
Value R/W Description
15 to 11 RFMBN4 to
RFMBN0
All 0 R Receive Byte Counter
The RFMBN value is incremented by 1 (+1) each
time a byte is received. However, when RFMBN
reaches B'10011, an overrun error occurs. At this
time, a receive data is not stored in CIRRDR.
When CIRRDR is read after the CIR has finished
receiving (CIRBUSY = 0), RFMBN is decremented
by 1 (
−
1). When CIRRDR is read while RFMBN =
B'00000, an undefined value is read. When CIRRDR
is read during the CIR reception, an undefined value
is read and RFMBN is not decremented.
10

0 R/W Reserved
The initial value should not be changed.
9 to 0 HHMIN9 to
HHMIN0 All 0 R/W Specifies the minimum high-level period for a header
or repeat header and the minimum low-level period
for a stop.