Renesas H8S/2100 Series, Hardware Manual

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Section 22 A/D Converter
Rev. 1.00 Apr. 28, 2008 Page 727 of 994
REJ09B0452-0100
Section 22 A/D Converter
This LSI includes one unit (unit 0) of successive-approximation-type 10-bit A/D converter that
allows up to sixteen analog input channels to be selected. Figure 22.1 shows a block diagram for
unit 0.
22.1 Features
•
10-bit resolution
•
Input channels: Sixteen channels
•
Conversion cycle: 40 cycles (A/D conversion clock)
•
Two kinds of operating modes
Single mode: Single-channel A/D conversion
Scan mode: Continuous A/D conversion on one to four channels or continuous A/D conversion
on one to eight channels
•
A/D conversion clocks specifiable (
φ
,
φ
/2,
φ
/4, or
φ
/8)
•
Eight data registers
Conversion results are held in a 16-bit data register for each channel
•
Sample and hold function
•
Three kinds of A/D conversion start
Software
Conversion start trigger from 16-bit timer pulse unit (TPU) or 8-bit timer (TMR)
•
Interrupt source
A/D conversion end interrupt (ADI) request can be generated