Renesas H8S/2100 Series, Hardware Manual

Page: 869 / 1024

Section 26 Power-Down Modes
Rev. 1.00 Apr. 28, 2008 Page 843 of 994
REJ09B0452-0100
Bit Bit Name
Initial
Value R/W
Description
2
1
0
SCK2
SCK1
SCK0
0
0
0
R/W
R/W
R/W
System Clock Select 2 to 0
These bits select a clock for the bus master in high-
speed mode or medium-speed mode.
When making a transition to watch mode, these bits
must be cleared to B'000.
000: High-speed mode
001: Medium-speed clock:
φ
/2
010: Medium-speed clock:
φ
/4
011: Medium-speed clock:
φ
/8
100: Medium-speed clock:
φ
/16
101: Medium-speed clock:
φ
/32
11X: Setting prohibited
[Legend]
X: Don’t care
Table 26.2 Operating Frequency and Wait Time
STS2 STS1 STS0 Wait Time 20 MHz 10 MHz 8 MHz Unit
0 0 0 8192 states 0.4 0.8 1.0
0 0 1 16384 states 0.8 1.6 2.0
0 1 0 32768 states 1.6 3.3 4.1
0 1 1 65536 states 3.3 6.6 8.2
1 0 0 131072 states 6.6 13.1 16.4
1 0 1 262144 states 13.1 26.2 32.8
ms
1 1 0/1 Reserved *
   
Recommended specification
Note: * Setting prohibited.