Section 20 LPC Interface (LPC)
Rev. 1.00 Apr. 28, 2008 Page 615 of 994
REJ09B0452-0100
Section 20 LPC Interface (LPC)
This LSI has an on-chip LPC interface.
The LPC includes four register sets, each of which comprises data and status registers, control
register, the fast Gate A20 logic circuit, and the host interrupt request circuit.
The LPC performs serial transfer of cycle type, address, and data, synchronized with the 33 MHz
PCI clock. It uses four signal lines for address/data and one for host interrupt requests. This LPC
module supports I/O read and I/O write cycle transfers. It is also provided with power-down
functions that can control the PCI clock and shut down the LPC interface.
20.1 Features
•
Supports LPC interface I/O read and I/O write cycles
Uses four signal lines (LAD3 to LAD0) to transfer the cycle type, address, and data.
Uses three control signals: clock (LCLK), reset (
LRESET
), and frame (
LFRAME
).
•
Four register sets comprising data and status registers
The basic register set comprises three bytes: an input register (IDR), output register (ODR),
and status register (STR).
I/O addresses from H'0000 to H'FFFF are selected for channels 1 to 4.
A fast Gate A20 function is provided for channel 1.
For channel 3, sixteen bidirectional data register bytes can be manipulated in addition to
the basic register set.
•
Supports SCIF
The LPC interface is connected to the SCIF, allowing direct control of the SCIF by the
LPC host.
•
Supports SERIRQ
Host interrupt requests are transferred serially on a single signal line (SERIRQ).
On channel 1, HIRQ1 and HIRQ12 can be generated.
On channels 2, 3 and 4, SMI, HIRQ6, and HIRQ9 to HIRQ11 can be generated.
In the SCIF, HIRQ1, SMI, and HIRQ3 to HIRQ15 can be generated.
Operation can be switched between quiet mode and continuous mode.
The
CLKRUN
signal can be manipulated to restart the PCI clock (LCLK).
•
Power-down modes and interrupts
The LPC module can be shut down by inputting the
LPCPD
signal.
Three pins,
PME
,
LSMI
, and LSCI, are provided for general input/output.
Summary of Contents for H8S/2100 Series
Page 2: ...Rev 1 00 Apr 28 2008 Page ii of xxvi...
Page 54: ...Section 1 Overview Rev 1 00 Apr 28 2008 Page 28 of 994 REJ09B0452 0100...
Page 92: ...Section 2 CPU Rev 1 00 Apr 28 2008 Page 66 of 994 REJ09B0452 0100...
Page 158: ...Section 5 Interrupt Controller Rev 1 00 Apr 28 2008 Page 132 of 994 REJ09B0452 0100...
Page 244: ...Section 8 8 Bit PWM Timer PWMU Rev 1 00 Apr 28 2008 Page 218 of 994 REJ09B0452 0100...
Page 330: ...Section 10 16 Bit Timer Pulse Unit TPU Rev 1 00 Apr 28 2008 Page 304 of 994 REJ09B0452 0100...
Page 416: ...Section 13 8 Bit Timer TMR Rev 1 00 Apr 28 2008 Page 390 of 994 REJ09B0452 0100...
Page 612: ...Section 18 I 2 C Bus Interface IIC Rev 1 00 Apr 28 2008 Page 586 of 994 REJ09B0452 0100...
Page 706: ...Section 20 LPC Interface LPC Rev 1 00 Apr 28 2008 Page 680 of 994 REJ09B0452 0100...
Page 752: ...Section 21 FSI Interface Rev 1 00 Apr 28 2008 Page 726 of 994 REJ09B0452 0100...
Page 774: ...Section 23 RAM Rev 1 00 Apr 28 2008 Page 748 of 994 REJ09B0452 0100...
Page 1008: ...Section 28 Electrical Characteristics Rev 1 00 Apr 28 2008 Page 982 of 994 REJ09B0452 0100...
Page 1020: ...Rev 1 00 Apr 28 2008 Page 994 of 994 REJ09B0452 0100...
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