Renesas H8S/2100 Series, Hardware Manual

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Section 15 Serial Communication Interface (SCI)
Rev. 1.00 Apr. 28, 2008 Page 423 of 994
REJ09B0452-0100
Table 15.8 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)
φ
(MHz)
External Input
Clock (MHz) Maximum Bit
Rate (bit/s)
φ
(MHz)
External Input
Clock (MHz) Maximum Bit
Rate (bit/s)
8 1.3333 1333333.3 16 2.6667 2666666.7
10 1.6667 1666666.7 18 3.0000 3000000.0
12 2.0000 2000000.0 20 3.3333 3333333.3
14 2.3333 2333333.3
Table 15.9 BRR Settings for Various Bit Rates (Smart Card Interface Mode, n = 0, s = 372)
Operating Frequency
φ
(MHz)
10.00 13.00 14.2848 16.00
Bit Rate
(bit/s)
n N Error
(%)
n N Error
(%)
n N Error (%) n N Error
(%)
9600 0 1 30 0 1 -8.99 0 1 0.00 0 1 12.01
Operating Frequency
φ
(MHz)
18.00 20.00
Bit Rate
(bit/s)
n N Error
(%)
n N Error
(%)
9600 0 2 -15.99 0 2 -6.65
Table 15.10 Maximum Bit Rate for Each Frequency (Smart Card Interface Mode, S = 372)
φ
(MHz)
Maximum Bit
Rate
(bit/s)
n N
φ
(MHz)
Maximum Bit
Rate
(bit/s)
n N
10.00 13441 0 0 16.00 21505 0 0
13.00 17473 0 0 18.00 24194 0 0
14.2848 19200 0 0 20.00 26882 0 0