Renesas H8S/2100 Series, Hardware Manual

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Section 18 I
2
C Bus Interface (IIC)
Rev. 1.00 Apr. 28, 2008 Page 582 of 994
REJ09B0452-0100
18.6 Usage Notes
1. In master mode, if an instruction to generate a start condition is issued and then an instruction
to generate a stop condition is issued before the start condition is output to the I
2
C bus, neither
condition will be output correctly.
2. Either of the following two conditions will start the next transfer. Pay attention to these
conditions when accessing ICDR.

Write to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from ICDRT to
ICDRS)

Read from ICDR when ICE = 1 and TRS = 0 (including automatic transfer from ICDRS to
ICDRR)
3. Table 18.9 shows the timing of SCL and SDA outputs in synchronization with the internal
clock. Timings on the bus are determined by the rise and fall times of signals affected by the
bus load capacitance, series resistance, and parallel resistance.
Table 18.9 I
2
C Bus Timing (SCL and SDA Outputs)
Item Symbol Output Timing Unit Notes
SCL output cycle time t
SCLO
28t
cyc
to 256t
cyc
ns
SCL output high pulse width t
SCLHO
0.5t
SCLO
ns
SCL output low pulse width t
SCLLO
0.5t
SCLO
ns
SDA output bus free time t
BUFO
0.5t
SCLO
– 1t
cyc
ns
Start condition output hold time t
STAHO
0.5t
SCLO
– 1t
cyc
ns
Retransmission start condition output
setup time t
STASO
1t
SCLO
ns
Stop condition output setup time t
STOSO
0.5t
SCLO
+ 2t
cyc
ns
Data output setup time (master) 1t
SCLLO
– 3t
cyc
Data output setup time (slave)
t
SDASO
1t
SCLL
– (6t
cyc
or
12t
cyc
*
)
ns
Data output hold time t
SDAHO
3t
cyc
ns
See figure
28.24 (for
reference)
Note:
*
6t
cyc
when IICX is 0, 12t
cyc
when 1.