Renesas H8S/2100 Series, Hardware Manual

Page: 19 / 1024

Rev. 1.00 Apr. 28, 2008 Page xix of xxvi
15.7.8 Clock Output Control............................................................................................ 458
15.8 Interrupt Sources................................................................................................................ 460
15.8.1 Interrupts in Normal Serial Communication Interface Mode ............................... 460
15.8.2 Interrupts in Smart Card Interface Mode .............................................................. 461
15.9 Usage Notes ....................................................................................................................... 462
15.9.1 Module Stop Mode Setting ................................................................................... 462
15.9.2 Break Detection and Processing ........................................................................... 462
15.9.3 Mark State and Break Sending.............................................................................. 462
15.9.4 Receive Error Flags and Transmit Operations
(Clocked Synchronous Mode Only) ..................................................................... 462
15.9.5 Relation between Writing to TDR and TDRE Flag .............................................. 462
15.9.6 SCI Operations during Mode Transitions ............................................................. 463
15.9.7 Notes on Switching from SCK Pins to Port Pins .................................................. 466
15.9.8 Note on Writing to Registers in Transmission, Reception, and
Simultaneous Transmission and Reception .......................................................... 467
Section 16 CIR Interface....................................................................................469
16.1 Features.............................................................................................................................. 469
16.2 Input Pins ........................................................................................................................... 471
16.3 Register Description........................................................................................................... 471
16.3.1 Receive Control Register 1 (CCR1)...................................................................... 472
16.3.2 Receive Control Register 2 (CCR2)...................................................................... 473
16.3.3 Receive Status Register (CSTR) ........................................................................... 474
16.3.4 Interrupt Enable Register (CEIR) ......................................................................... 476
16.3.5 Bit Rate Register (BRR) ....................................................................................... 477
16.3.6 Receive Data Register 0 to 17 (CIRRDR0 to CIRRDR17) .................................. 478
16.3.7 Header Minimum/Maximum High-Level Period Register
(HHMIN and HHMAX) ....................................................................................... 478
16.3.8 Header Minimum/Maximum Low-Level Period Register
(HLMIN/HLMAX) ............................................................................................... 480
16.3.9 Data Level 1 Minimum/Maximum Period Register
(DT1MIN/DT1MAX) ....................................................................................... 480
16.3.10 Data Level 0 Minimum/Maximum Period Register
(DT0MIN/DT0MAX) ........................................................................................... 481
16.3.11 Repeat Header Minimum/Maximum Low-Level Period Register
(RMIN/RMAX) .................................................................................................... 481
16.4 Operation ........................................................................................................................... 482
16.4.1 Determination of Signal Type by Low/High-Level Period................................... 484
16.4.2 Operation of FIFO Register .................................................................................. 486
16.4.3 Operation in Watch Mode..................................................................................... 487