Renesas H8S/2100 Series, Hardware Manual

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Section 4 Exception Handling
Rev. 1.00 Apr. 28, 2008 Page 75 of 994
REJ09B0452-0100
Section 4 Exception Handling
4.1 Exception Handling Types and Priority
As table 4.1 indicates, exception handling may be caused by a reset, illegal instruction, interrupt,
direct transition, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two
or more exceptions occur simultaneously, they are accepted and processed in order of priority.
Table 4.1 Exception Types and Priority
Priority Exception Type Start of Exception Handling
Reset Starts immediately after a low-to-high transition of the
RES
pin, or when the watchdog timer overflows.
Illegal instruction Exception handling starts when an undefined code is
executed.
Interrupt Starts when execution of the current instruction or exception
handling ends, if an interrupt request has been issued.
Interrupt detection is not performed on completion of ANDC,
ORC, XORC, or LDC instruction execution, or on
completion of reset exception handling.
High
Direct transition Starts when a direct transition occurs as the result of
SLEEP instruction execution.
Low Trap instruction Started by execution of a trap (TRAPA) instruction. Trap
instruction exception handling requests are accepted at all
times in the program execution state.