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Renesas H8S/2100 Series, Hardware Manual

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Section 12   16-Bit Duty Period Measurement Timer (TDP) 

Rev. 1.00  Apr. 28, 2008  Page 352 of 994 

REJ09B0452-0100 

 

12.6.3 Conflict 

between 

Input Capture and TDPICR Read 

When the corresponding input capture signal is detected during reading of TDPICR in timer mode, 
the input capture signal is delayed by one cycle of the system clock (

φ

). Figure 12.15 shows the 

timing of this conflict. 

φ

TDPCYI

TDPICR
read signal 

TDPICR

ICPF

Input capture
signal

N + 2

N + 1

N

Capture occurs

N - 1

N

M

TDPCNT

 

Figure 12.15   Conflict between Input Capture and TDPICR Read 

12.6.4 

Conflict between Edge Detection in Cycle Measurement Mode and Writing to the 

Upper Limit or Lower Limit Register 

If the edge of TDPCYI is detected in the second half of a cycle of writing to any of the upper 
limit/lower limit registers (TDPPDMX, TDPPDMN, TDPWDMX, and TDPWDMN) in cycle 
measurement mode, the detected edge signal is delayed by one cycle of the system clock (

φ

). 

Figure 12.16 shows the timing of this conflict. 

TDPICR > TDPPDMX (Cycle upper limit exceeded)

Capture occurs

φ

TDPCYI

Internal write
signal

TDPICR

TPDMXOVF

Input capture
signal

N

M

H'0000

N

TDPCNT

 

Figure 12.16   Conflict between Edge Detection and Register Write  

(Cycle Measurement Mode) 

Summary of Contents for H8S/2100 Series

Page 1: ...Group All information contained in this material including products and product specifications at the time of publication of this material is subject to change by Renesas Technology Corp without noti...

Page 2: ...Rev 1 00 Apr 28 2008 Page ii of xxvi...

Page 3: ...ty and reliability such as safety systems or equipment or systems for transportation and traffic healthcare combustion control aerospace and aeronautics nuclear power or undersea communication transmi...

Page 4: ...when power is supplied until the reset process is completed In a similar way the states of pins in a product that is reset by an on chip power on reset function are not guaranteed from the moment when...

Page 5: ...a summary of major points of revision or addition for earlier versions It does not cover all revised items For details on the revised points see the actual locations in the manual The following docume...

Page 6: ...e 1 Overall notation 2 Register notation Rev 0 50 10 04 page 416 of 914 14 2 2 Compare Match Control Status Register_0 _1 CMCSR_0 CMCSR_1 14 3 1 Interval Count Operation 4 3 2 Binary numbers are given...

Page 7: ...al value is 1 The initial value is undefined 3 Initial value For each bit and bit field this entry indicates whether the bit or field is readable or writable or both writing to and reading from the bi...

Page 8: ...erface adapter bps Bits per second CRC Cyclic redundancy check DMA Direct memory access DMAC Direct memory access controller GSM Global System for Mobile Communications Hi Z High impedance IEBus Inter...

Page 9: ...0H CPU 31 2 2 CPU Operating Modes 32 2 2 1 Normal Mode 32 2 2 2 Advanced Mode 34 2 3 Address Space 36 2 4 Registers 37 2 4 1 General Registers 38 2 4 2 Program Counter PC 39 2 4 3 Extended Control Reg...

Page 10: ...ection 67 3 2 Register Descriptions 68 3 2 1 Mode Control Register MDCR 68 3 2 2 System Control Register SYSCR 69 3 2 3 Serial Timer Control Register STCR 71 3 2 4 System Control Register 3 SYSCR3 73...

Page 11: ...terrupt Status Register WUESR Wake Up Enable Register WER 104 5 4 Interrupt Sources 105 5 4 1 External Interrupt Sources 105 5 4 2 Internal Interrupt Sources 108 5 5 Interrupt Exception Handling Vecto...

Page 12: ...n A to D and F to J 149 7 1 6 Noise Canceler Enable Register PnNCE n 6 C and G 149 7 1 7 Noise Canceler Decision Control Register PnNCMC n 6 C and G 150 7 1 8 Noise Cancel Cycle Setting Register PnNC...

Page 13: ...s 210 8 4 2 Pulse Division Mode 214 8 5 Usage Note 217 8 5 1 Setting Module Stop Mode 217 8 5 2 Note on Using 16 Bit Single Pulse PWM Timer 217 Section 9 14 Bit PWM Timer PWMX 219 9 1 Features 219 9 2...

Page 14: ...Operation Timing 290 10 7 1 Input Output Timing 290 10 7 2 Interrupt Signal Timing 294 10 8 Usage Notes 297 10 8 1 Input Clock Restrictions 297 10 8 2 Caution on Period Setting 297 10 8 3 Conflict be...

Page 15: ...Conflict between TCMMLCM Write and Compare Match 325 11 6 3 Conflict between TCMICR Read and Input Capture 326 11 6 4 Conflict between Edge Detection in Cycle Measurement Mode and Writing to TCMMLCM o...

Page 16: ...for TDPCKI and TDPMCI 353 12 6 7 Setting for Module Stop Mode 353 Section 13 8 Bit Timer TMR 355 13 1 Features 355 13 2 Input Output Pins 358 13 3 Register Descriptions 359 13 3 1 Timer Counter TCNT...

Page 17: ...onflict between Compare Matches A and B 386 13 9 5 Switching of Internal Clocks and TCNT Operation 387 13 9 6 Mode Setting with Cascaded Connection 389 13 9 7 Module Stop Mode Setting 389 Section 14 W...

Page 18: ...l Data Transmission Asynchronous Mode 429 15 4 6 Serial Data Reception Asynchronous Mode 431 15 5 Multiprocessor Communication Function 435 15 5 1 Multiprocessor Serial Data Transmission 437 15 5 2 Mu...

Page 19: ...Reception 467 Section 16 CIR Interface 469 16 1 Features 469 16 2 Input Pins 471 16 3 Register Description 471 16 3 1 Receive Control Register 1 CCR1 472 16 3 2 Receive Control Register 2 CCR2 473 16...

Page 20: ...IR 500 17 3 8 FIFO Control Register FFCR 502 17 3 9 Line Control Register FLCR 503 17 3 10 Modem Control Register FMCR 504 17 3 11 Line Status Register FLSR 506 17 3 12 Modem Status Register FMSR 510...

Page 21: ...State 579 18 5 Interrupt Sources 581 18 6 Usage Notes 582 18 6 1 Module Stop Mode Setting 585 Section 19 Keyboard Buffer Control Unit PS2 587 19 1 Features 587 19 2 Input Output Pins 589 19 3 Registe...

Page 22: ...20 3 7 LPC Channel 3 Address Registers H and L LADR3H and LADR3L 634 20 3 8 LPC Channel 4 Address Registers H and L LADR4H and LADR4L 636 20 3 9 Input Data Registers 1 to 4 IDR1 to IDR4 637 20 3 10 O...

Page 23: ...693 21 3 10 FSI Access Host Base Address Registers H and L FSIHBARH and FSIHBARL 694 21 3 11 FSI Flash Memory Size Register FSISR 694 21 3 12 FSI Command Host Base Address Registers H and L CMDHBARH a...

Page 24: ...es 741 22 7 1 Module Stop Mode Setting 741 22 7 2 Permissible Signal Source Impedance 741 22 7 3 Influences on Absolute Accuracy 742 22 7 4 Setting Range of Analog Power Supply and Other Pins 742 22 7...

Page 25: ...xternal Clock Input Method 835 25 2 Duty Correction Circuit 838 25 3 Subclock Input Circuit 838 25 4 Subclock Waveform Forming Circuit 839 25 5 Clock Select Circuit 839 25 6 Usage Notes 840 25 6 1 Not...

Page 26: ...934 Section 28 Electrical Characteristics 957 28 1 Absolute Maximum Ratings 957 28 2 DC Characteristics 958 28 3 AC Characteristics 963 28 3 1 Clock Timing 964 28 3 2 Control Signal Timing 966 28 3 3...

Page 27: ...H and H8S As peripheral functions each LSI of the group includes a serial communication interface with FIFO an I2 C bus interface an A D converter and various types of timers Together the modules real...

Page 28: ...CPUs at object level General register architecture sixteen 16 bit general registers Eight addressing modes 4 Gbyte address space Program 4 Gbytes available Data 4 Gbytes available 69 basic instruction...

Page 29: ...to ExIRQ6 KIN15 to KIN0 and WUE15 to WUE8 66 internal interrupt sources Two interrupt control modes specified by the system control register Two levels of interrupt priority orders specifiable by sett...

Page 30: ...r operation Multiple timer counters TCNT can be written to simultaneously Simultaneous clearing by compare match and input capture possible Register simultaneous input output possible by counter synch...

Page 31: ...onous or clocked synchronous serial communication mode Full duplex communication capability Selection of the desired bit rate and LSB first or MSB first transfer Smart card SIM Serial communi cation i...

Page 32: ...128 pins BP 176V 76 pull up resistors for TFP 144V and TLP 145V and 84 pull up resistors for BP 176V 40 pins with LED drive capability 24 on chip noise cancellers Package 144 pin thin QFP package PTQP...

Page 33: ...oducts Part No ROM Capacity RAM Capacity Package Remarks R4F2117R 160 Kbytes 8 Kbytes PTQP0144LC A PLBG0176GA A PTLG0145JB A Flash memory version Part no R 4 F 2117R Indicates the product specific num...

Page 34: ...I0 TxD2 TCMCYI0 P41 TMO0 RxD2 TCMCKI0 TCMMCI0 P42 SDA1 TCMCYI1 P43 TMI1 SCK2 TCMCKI1 TCMMCI1 P44 TMO1 PWMU2B TCMCYI2 P45 PWMU3B TCMCKI2 TCMMCI2 P46 PWX0 PWMU4B TCMCYI3 P47 PWX1 PWMU5B TCMCKI3 TCMMCI3...

Page 35: ...21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 99 98 97 96 95 94 93 92 91 90 89 88 87 86 8...

Page 36: ...P84 PJ0 PH3 P43 P45 P47 P22 P21 P20 P16 PB7 PB2 P30 P34 P37 P83 P42 PH4 P46 VSS VSS P77 P74 P72 AVSS PD1 PD4 PG0 PG3 PG6 PF1 PF6 VSS PA1 VCC VCC AVCC AVCC P76 P70 PD3 PD6 PG2 PI0 PI1 PF3 PF7 NC PA3 PA...

Page 37: ...D1 PD6 P31 P30 PD0 P27 P72 P70 VSS PC4 P65 PD2 P17 VCC PB3 P71 P21 AVref P73 P23 PC0 P66 P62 P14 PC6 PB7 AVCC P25 P77 P74 PC2 PC5 P63 P61 P22 P67 P12 P75 P24 P60 P76 P26 PC1 PC7 P64 P20 PC3 P11 PA3 PH...

Page 38: ...TCMCKI1 TCMMCI1 3 B1 C2 P44 TMO1 PWMU2B TCMCYI2 4 C2 B2 P45 PWMU3B TCMCKI2 TCMMCI2 5 D3 C1 P46 PWX0 PWMU4B TCMCYI3 6 C1 C3 P47 PWX1 PWMU5B TCMCKI3 TCMMCI3 7 D2 D2 VSS E4 NC 8 E3 D3 RES D1 VSS 9 E2 D1...

Page 39: ...ST 28 T L2 T K4 T PE4 ETMS 29 L4 J1 PE3 ETDO 30 T M1 T K2 T PE2 ETDI 31 T M2 T J3 T PE1 ETCK 32 T M3 T K1 T PE0 ExEXCL 33 N N1 N L2 N PA7 KIN15 PS2CD 34 N M4 N K3 N PA6 KIN14 PS2CC 35 N N2 N L1 N PA5...

Page 40: ...1 N R7 N L6 N PG7 ExIRQ15 ExSCLB 52 N P7 N M7 N PG6 ExIRQ14 ExSDAB 53 N M8 N N6 N PG5 ExIRQ13 ExSCLA N8 N PI0 54 N R8 N K6 N PG4 ExIRQ12 ExSDAA 55 N P8 N K7 N PG3 ExIRQ11 SCL2 M9 N NC 56 N N9 N K8 N P...

Page 41: ...75 P15 L12 P77 AN7 76 N14 M12 AVCC M13 NC N15 AVCC 77 M14 L11 AVref L12 E5 NC M15 AVref 78 L13 L13 P60 KIN0 79 L14 K12 P61 KIN1 80 L15 K11 P62 KIN2 81 K12 J12 P63 KIN3 82 K13 K13 P64 KIN4 K15 PJ7 83 K...

Page 42: ...PC0 TIOCA0 WUE8 95 F12 F10 VSS F13 VSS F15 PJ5 96 F14 E10 P27 97 E13 F13 P26 98 E15 E12 P25 99 E14 E13 P24 100 E12 F11 P23 101 D15 D12 P22 102 D14 E11 P21 103 D13 D13 P20 104 C15 D10 P17 105 D12 C12 P...

Page 43: ...21 D9 A9 P30 LAD0 122 C9 D9 P31 LAD1 123 A9 C8 P32 LAD2 124 B9 B7 P33 LAD3 125 D8 A8 P34 LFRAME 126 C8 D8 P35 LRESET 127 A8 D7 P36 LCLK B8 PJ1 128 D7 D6 P37 SERIRQ 129 C7 A7 P80 PME 130 A7 B6 P81 GA20...

Page 44: ...176V TLP 145V Mode 2 EXPE 0 A3 NC 141 D4 B3 PH4 142 B3 C4 PH5 143 A2 A3 XTAL 144 B2 A2 EXTAL Notes N in Pin No indicates the pin is driven by NMOS push pull open drain and has 5 V input tolerance T in...

Page 45: ...4 R4 F12 F13 B13 A13 A4 B4 D2 L3 F10 B11 C5 Input Ground pins Connect all these pins to the system power supply 0 V XTAL 143 A2 A3 Input EXTAL 144 B2 A2 Input For connection to a crystal resonator An...

Page 46: ...3 Input ETMS 28 L2 K4 Input ETDO 29 L4 J1 Output ETDI 30 M1 K2 Input H UDI ETCK 31 M2 J3 Input Interface pins for emulator Reset by holding the ETRST pin to low level regardless of the H UDI activatio...

Page 47: ...tput PWM output pins for TGRA_2 and TGRB_2 TCMCKI3 to TCMCKI0 6 4 2 137 C1 C2 C3 B5 C3 B2 A1 A5 Input Timer external clock input pins TCMMCI3 to TCMMCI0 6 4 2 137 C1 C2 C3 B5 C3 B2 A1 A5 Input Cycle m...

Page 48: ...ut pins for the keyboard buffer control unit Keyboard buffer control unit PS2 PS2AD PS2BD PS2CD PS2DD 38 35 33 40 N3 N2 N1 P3 M2 L1 L2 N1 Input Output Data input output pins for the keyboard buffer co...

Page 49: ...121 B9 A9 C9 D9 B7 C8 D9 A9 Input Output LPC command address and data input output pins LFRAME 125 D8 A8 Input Input pin indicating LPC cycle start and forced termination of an abnormal LPC cycle LRES...

Page 50: ...5 to 68 M10 N10 R10 P10 N11 R11 P11 M11 P15 N13 R15 P14 R14 P13 R13 N12 L7 K9 N8 M9 L8 K10 N9 M10 L12 N13 M13 N12 N11 L10 M11 N10 Input Analog input pins AVCC 76 N14 N15 M12 Input Analog power supply...

Page 51: ...ted from the SDA0 SDA1 ExSDAA and ExSDAB pins P17 to P10 104 to 110 112 C15 D12 C14 B15 B14 A15 C13 B12 D10 C12 C13 D11 B13 A12 A13 B12 Input Output 8 bit input output pins P27 to P20 96 to 103 F14 E1...

Page 52: ...2 M2 M3 N1 N3 Input Output 8 bit input output pins The output type of PA7 to PA0 is NMOS push pull PB7 to PB0 113 to 120 D11 A12 C11 B11 A11 D10 A10 B10 A11 C11 B10 C10 A10 B9 C9 B8 Input Output 8 bit...

Page 53: ...to PJ0 K15 J14 F15 A14 C12 C10 B8 C5 Input Output 8 bit input output pins Notes 1 Pins PE4 to PE1 are not supported by the system development tool emulator 2 Following precautions are required on the...

Page 54: ...Section 1 Overview Rev 1 00 Apr 28 2008 Page 28 of 994 REJ09B0452 0100...

Page 55: ...egister architecture Sixteen 16 bit general registers also usable as sixteen 8 bit registers or eight 32 bit registers Sixty nine basic instructions 8 16 32 bit arithmetic and logic instructions Multi...

Page 56: ...own below Register configuration The MAC register is supported by the H8S 2600 CPU only Basic instructions The four instructions MAC CLRMAC LDMAC and STMAC are supported by the H8S 2600 CPU only The n...

Page 57: ...igned multiply and divide instructions have been added A multiply and accumulate instruction has been added Two bit shift instructions have been added Instructions for saving and restoring multiple re...

Page 58: ...e used Only the lower 16 bits of effective addresses EA are valid Exception Vector Table and Memory Indirect Branch Addresses In normal mode the top area starting at H 0000 is allocated to the excepti...

Page 59: ...ion vector 3 Exception vector 5 Exception vector 6 Exception vector table Exception vector 4 Figure 2 1 Exception Vector Table Normal Mode PC 16 bits EXR 1 Reserved 1 3 CCR CCR 3 PC 16 bits SP SP SP 2...

Page 60: ...ndirect Branch Addresses In advanced mode the top area starting at H 00000000 is allocated to the exception vector table in units of 32 bits In each 32 bits the upper 8 bits are ignored and a branch a...

Page 61: ...e that the first part of this range is also used for the exception vector table Stack Structure In advanced mode when the program counter PC is pushed onto the stack in a subroutine call and the PC co...

Page 62: ...s space in normal mode and a maximum 16 Mbyte architecturally 4 Gbyte address space in advanced mode The usable modes and address spaces differ depending on the product For details on each product ref...

Page 63: ...ACH MACL MAC 23 63 32 41 31 0 0 15 0 7 0 7 0 E0 E1 E2 E3 E4 E5 E6 E7 R0H R1H R2H R3H R4H R5H R6H R7H R0L R1L R2L R3L R4L R5L R6L R7L SP PC EXR T I2 to I0 CCR I UI Stack pointer Program counter Extende...

Page 64: ...These registers are functionally equivalent providing a maximum of sixteen 16 bit registers The E registers E0 to E7 are also referred to as extended registers The R registers divide into 8 bit gener...

Page 65: ...it register that manipulates the LDC STC ANDC ORC and XORC instructions When these instructions except for the STC instruction are executed all interrupts including NMI will be masked for three states...

Page 66: ...rupt Mask Bit Can be read or written by software using the LDC STC ANDC ORC and XORC instructions This bit cannot be used as an interrupt mask bit in this LSI 5 H Undefined R W Half Carry Flag When th...

Page 67: ...lation instructions 2 4 5 Multiply Accumulate Register MAC This 64 bit register stores the results of multiply and accumulate operations It consists of two 32 bit registers denoted MACH and MACL The l...

Page 68: ...just instructions treat byte data as two digits of 4 bit BCD data 2 5 1 General Register Data Formats Figure 2 9 shows the data formats in general registers 7 0 7 0 MSB LSB MSB LSB 7 0 4 3 Don t care...

Page 69: ...SB En Rn ERn En Rn RnH RnL MSB LSB General register ER General register E General register R General register RH General register RL Most significant bit Least significant bit Data Type Data Format Re...

Page 70: ...ess an address error does not occur however the least significant bit of the address is regarded as 0 so access begins the preceding address This also applies to instruction fetches When ER7 is used a...

Page 71: ...STMAC CLRMAC Logic operations AND OR XOR NOT B W L 4 Shift SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR B W L 8 Bit manipulation BSET BCLR BNOT BTST BLD BILD BST BIST BAND BIAND BOR BIOR BXOR BIXOR B 14...

Page 72: ...stination Rs General register source Rn General register ERn General register 32 bit register MAC Multiply accumulate register 32 bit register EAd Destination operand EAs Source operand EXR Extended c...

Page 73: ...ister and memory or moves immediate data to a general register MOVFPE B Cannot be used in this LSI MOVTPE B Cannot be used in this LSI POP W L SP Rn Pops a general register from the stack POP W Rn is...

Page 74: ...2 Byte operands can be incremented or decremented by 1 only ADDS SUBS L Rd 1 Rd Rd 2 Rd Rd 4 Rd Adds or subtracts the value 1 2 or 4 to or from data in a 32 bit register DAA DAS B Rd decimal adjust Rd...

Page 75: ...a 32 bit register to longword size by padding with zeros on the left EXTS W L Rd sign extension Rd Extends the lower 8 bits of a 16 bit register to word size or the lower 16 bits of a 32 bit register...

Page 76: ...ata NOT B W L Rd Rd Takes the one s complement logical complement of general register contents Note Refers to the operand size B Byte W Word L Longword Table 2 6 Shift Instructions Instruction Size Fu...

Page 77: ...fied bit in a general register or memory operand and sets or clears the Z flag accordingly The bit number is specified by 3 bit immediate data or the lower three bits of a general register BAND BIAND...

Page 78: ...umber is specified by 3 bit immediate data BLD BILD B B bit No of EAd C Transfers a specified bit in a general register or memory operand to the carry flag bit No of EAd C Transfers the inverse of a s...

Page 79: ...r false Never BHI High C Z 0 BLS Low or same C Z 1 BCC BHS Carry clear high or same C 0 BCS BLO Carry set low C 1 BNE Not equal Z 0 BEQ Equal Z 1 BVC Overflow clear V 0 BVS Overflow set V 1 BPL Plus N...

Page 80: ...performed between them and memory The upper 8 bits are valid STC B W CCR EAd EXR EAd Transfers CCR or EXR contents to a general register or memory Although CCR and EXR are 8 bit registers word size t...

Page 81: ...V W if R4L 0 then Repeat ER5 ER6 R4L 1 R4L Until R4L 0 else next if R4 0 then Repeat ER5 ER6 R4 1 R4 Until R4 0 else next Transfers a data block Starting from the address set in ER5 transfers data for...

Page 82: ...Some instructions have two operation fields Register Field Specifies a general register Address registers are specified by 3 bits and data registers by 3 bits or 4 bits Some instructions have two reg...

Page 83: ...ddressing Mode Symbol 1 Register direct Rn 2 Register indirect ERn 3 Register indirect with displacement d 16 ERn d 32 ERn 4 Register indirect with post increment Register indirect with pre decrement...

Page 84: ...with pre decrement ERn The value 1 2 or 4 is subtracted from an address register ERn specified by the register field in the instruction code and the result is the address of a memory operand The resul...

Page 85: ...ion instructions contain 3 bit immediate data in the instruction code specifying a bit number The TRAPA instruction contains 2 bit immediate data in its instruction code specifying a vector address 2...

Page 86: ...s a longword operand the first byte of which is assumed to be 0 H 00 Note that the first part of the address range is also the exception vector area For further details refer to section 4 Exception Ha...

Page 87: ...ment d 16 ERn or d 32 ERn 4 r op disp r op rm op rn 31 0 31 0 r op Don t care 31 23 31 0 Don t care 31 0 disp 31 0 31 0 31 23 31 0 Don t care 31 23 31 0 Don t care 24 24 24 24 Addressing Mode and Inst...

Page 88: ...Mode and Instruction Format Absolute address Immediate Effective Address Calculation Effective Address EA Sign extension Operand is immediate data 31 23 7 Program counter relative d 8 PC d 16 PC Memor...

Page 89: ...r to section 4 Exception Handling The reset state can also be entered by a watchdog timer overflow Exception Handling State The exception handling state is a transient state that occurs when the CPU a...

Page 90: ...state is made whenever the RES pin goes low A transition can also be made to the reset state when the watchdog timer overflows The power down state also includes watch mode For details refer to sectio...

Page 91: ...byte units and write data in byte units after bit operation Therefore attention must be paid when these instructions are used for ports or registers including write only bits Instruction BCLR can be u...

Page 92: ...Section 2 CPU Rev 1 00 Apr 28 2008 Page 66 of 994 REJ09B0452 0100...

Page 93: ...6 1 1 0 Emulation On chip emulation mode Enabled Note MD0 is not available as a pin and is internally fixed to 0 Modes 2 is single chip mode Modes 0 1 3 5 and 7 are not available in this LSI Modes 4 a...

Page 94: ...e and to monitor the current operating mode Bit Bit Name Initial Value R W Description 7 EXPE 0 R W Reserved The initial value should not be changed 6 to 3 All 0 R Reserved The initial value should no...

Page 95: ...ese bits select the interrupt control mode of the interrupt controller For details on the interrupt control modes see section 5 6 Interrupt Control Modes and Interrupt Operation 00 Interrupt control m...

Page 96: ...NT_Y TCORC TCORA_X TCORB_X TCONRI and TCONRS of 8 bit timers TMR_X and TMR_Y 0 Enables CPU access for registers of TMR_X and TMR_Y in areas from H FF FFF0 to H FF FFF7 and from H FF FFFC to H FF FFFF...

Page 97: ...SR ICDR SARX ICMR SAR and ICRES PWMX registers DADRAH DACR DADRAL DADRBH DACNTH and DADRBL DACNTL and SCI registers SMR BRR and SCMR 0 SCI_1 registers are accessed in areas from H FF FF88 to H FF FF89...

Page 98: ...is reserved 1 When RELOCATE is 0 control registers of flash memory are accessed in an area from H FF FEA8 to H FF FEAE Area from H FF FF80 to H FF FF87 is reserved When RELOCATE is 1 control registers...

Page 99: ...OCATE 1 R W Register Address Map Select Selects compatible mode or extended mode for the register map When extended mode is selected for the register map CPU access for registers can be controlled wit...

Page 100: ...EXPE 0 Advanced mode Single chip mode H 027FFF H 0FFFFF H 000000 H 028000 Reserved area On chip ROM 160 Kbytes Internal I O registers 2 Internal I O registers 1 On chip RAM 128 bytes On chip RAM 8064...

Page 101: ...eset Starts immediately after a low to high transition of the RES pin or when the watchdog timer overflows Illegal instruction Exception handling starts when an undefined code is executed Interrupt St...

Page 102: ...de Reset 0 H 000000 to H 000003 Reserved for system use 1 3 H 000004 to H 000007 H 00000C to H 00000F Illegal instruction 4 H 000010 to H 000013 Reserved for system use 5 H 000014 to H 000017 Direct t...

Page 103: ...H 00007F H 000080 to H 000083 H 000084 to H 000087 Internal interrupt 34 55 H 000088 to H 00008B H 0000DC to H 0000DF External interrupt IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 56 57 58 59 60 6...

Page 104: ...rces 8 9 10 11 H 000020 to H 000023 H 000024 to H 000027 H 000028 to H 00002B H 00002C to H 00002F Reserved for system use 12 15 H 000030 to H 000033 H 00003C to H 00003F External interrupt IRQ0 IRQ1...

Page 105: ...ority When the RES pin goes low all processing halts and this LSI enters the reset state To ensure that this LSI is reset hold the RES pin low for at least 20 ms at power on To reset the chip during o...

Page 106: ...r a reset and before the stack pointer SP is initialized the PC and CCR will not be saved correctly leading to a program crash To prevent this all interrupt requests including NMI are disabled immedia...

Page 107: ...from that address 4 5 Trap Instruction Exception Handling Trap instruction exception handling starts when a TRAPA instruction is executed Trap instruction exception handling can be executed at all ti...

Page 108: ...tate of CCR after execution of illegal instruction exception handling Table 4 5 Status of CCR after Illegal Instruction Exception Handling CCR Interrupt Control Mode I UI 0 Set to 1 Retains the previo...

Page 109: ...tion Handling Figure 4 2 shows the stack after completion of trap instruction exception handling and interrupt exception handling SP CCR Normal mode SP CCR CCR PC 16 bits Advanced mode PC 24 bits Note...

Page 110: ...the following instructions to restore registers POP W Rn or MOV W SP Rn POP L ERn or MOV L SP ERn Setting SP to an odd value may lead to a malfunction Figure 4 3 shows an example of what occurs when t...

Page 111: ...ng edge rising edge or both edge detection or level sensing can be independently selected for IRQ15 to IRQ0 When the EIVS bit in the system control register 3 SYSCR3 is cleared to 0 the IRQ6 interrupt...

Page 112: ...ISCR IER KMIMR WUEMR ICR Interrupt controller Priority level determination Interrupt request Vector number I UI CCR CPU ICR ISCR IER ISR KMIMR WUEMR SYSCR SYSCR3 Interrupt control register IRQ sense c...

Page 113: ...askable external interrupt pins Rising edge falling edge or both edge detection or level sensing can be selected individually for each pin To which pin the IRQ15 to IRQ6 interrupt is input can be sele...

Page 114: ...er ABRKCR R W H FEF4 8 Break address registers A BARA R W H 00 H FEF5 8 Break address registers B BARB R W H 00 H FEF6 8 Break address registers C BARC R W H 00 H FEF7 8 IRQ sense control register 16H...

Page 115: ...ell when RELOCATE 1 2 Address in the upper cell when EIVS 0 address in the lower cell when EIVS 1 5 3 1 Interrupt Control Registers A to D ICRA to ICRD The ICR registers set interrupt control levels f...

Page 116: ...ICRn2 TMR_1 FSI TPU_1 1 ICRn1 WDT_0 TMR_X TMR_Y LPC FSI TPU_2 0 ICRn0 WDT_1 PS2 Note n A to D Reserved The initial value should not be changed Table 5 4 Correspondence between Interrupt Source and IC...

Page 117: ...Undefined R Condition Match Flag Address break source flag Indicates that an address specified by BARA to BARC is prefetched Clearing condition When an exception handling is executed for an address b...

Page 118: ...cription 7 to 0 A23 to A16 All 0 R W Addresses 23 to 16 The A23 to A16 bits are compared with A23 to A16 in the internal address bus BARB Bit Bit Name Initial Value R W Description 7 to 0 A15 to A8 Al...

Page 119: ...W R W 5 4 IRQ14SCB IRQ14SCA 0 0 R W R W 3 2 IRQ13SCB IRQ13SCA 0 0 R W R W 1 0 IRQ12SCB IRQ12SCA 0 0 R W R W IRQn Sense Control B IRQn Sense Control A BA 00 Interrupt request generated at low level of...

Page 120: ...dges of IRQn or ExIRQn input n 11 to 8 Note The IRQn or ExIRQn pin is selected by IRQ sense port select register 16 ISSR16 ISCRH Bit Bit Name Initial Value R W Description 7 6 IRQ7SCB IRQ7SCA 0 0 R W...

Page 121: ...0 R W R W 3 2 IRQ1SCB IRQ1SCA 0 0 R W R W 1 0 IRQ0SCB IRQ0SCA 0 0 R W R W IRQn Sense Control B IRQn Sense Control A BA 00 Interrupt request generated at low level of IRQn input 01 Interrupt request g...

Page 122: ...on 7 6 5 4 3 2 1 0 IRQ15E IRQ14E IRQ13E IRQ12E IRQ11E IRQ10E IRQ9E IRQ8E 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W IRQn Enable The IRQn interrupt request is enabled when this bit is 1 n 15 to 8...

Page 123: ...W R W R W R W R W R W R W R W Setting condition When the interrupt source selected by the ISCR16 registers occurs Clearing conditions When writing 0 to IRQnF flag after reading IRQnF 1 When interrupt...

Page 124: ...ISCR registers occurs Clearing conditions When writing 0 to IRQnF flag after reading IRQnF 1 When interrupt exception handling is executed when low level detection is set and IRQn or ExIRQn input is...

Page 125: ...bles a key sensing input interrupt request 1 Disables a key sensing input interrupt request KMIMR Bit Bit Name Initial Value R W Description 7 6 5 4 3 2 1 0 KMIMR7 KMIMR6 KMIMR5 KMIMR4 KMIMR3 KMIMR2 K...

Page 126: ...5 4 3 2 1 0 WUEMR15 WUEMR14 WUEMR13 WUEMR12 WUEMR11 WUEMR10 WUEMR9 WUEMR8 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W Wake Up Event Interrupt Mask These bits enable or disable a wake up event inp...

Page 127: ...6 P67 KIN7 IRQ7 KMIMR8 Initial value of 1 PA0 KIN8 KMIMR9 Initial value of 1 PA1 KIN9 KMIMR15 Initial value of 1 PA7 KIN15 IRQ6 interrupt IRQ7 interrupt IRQ6 internal signal Edge level selection enabl...

Page 128: ...enable disable circuit IRQ7 interrupt Edge level selection enable disable circuit KINA interrupt KIN15 to KIN8 KINA internal signal KMIMR0 Initial value of 1 KMIMR5 Initial value of 1 KMIMR6 Initial v...

Page 129: ...4 0 R W 0 P95 IRQ14 is selected 1 PG6 ExIRQ14 is selected 5 ISS13 0 R W 0 P94 IRQ13 is selected 1 PG5 ExIRQ13 is selected 4 ISS12 0 R W 0 P93 IRQ12 is selected 1 PG4 ExIRQ12 is selected 3 ISS11 0 R W...

Page 130: ...t Interrupt Source Select These bits select the source that generates an interrupt request at wake up event interrupt inputs WUE15 to WUE8 0 Interrupt request generated at falling edge of WUEn input 1...

Page 131: ...lways accepted regardless of the interrupt control mode or the status of the CPU interrupt mask bits The NMIEG bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or...

Page 132: ...A IRQnSCB n 15 to 7 m 15 to 7 Note Switching between the IRQ6 and ExIRQ6 pins is controlled by the EIVS bit Edge level detection circuit Figure 5 4 Block Diagram of Interrupts IRQ15 to IRQ0 3 KIN15 to...

Page 133: ...y input to the ExIRQ6 pin The IRQ6 pin is only available for a KIN interrupt input and functions as the KIN6 pin The initial value of the KMIMR6 bit is 1 For the IRQ7 interrupt either the IRQ7 pin or...

Page 134: ...the EIVS bit in system control register 3 SYSCR3 For default priorities the lower the vector number the higher the priority Modules set at the same priority will conform to their default priorities Pr...

Page 135: ...ut capture compare match TGI0D TGR0D input capture compare match TGI0V Overflow 0 34 35 36 37 38 H 000088 H 00008C H 000090 H 000094 H 000098 ICRD3 TPU_1 TGI1A TGR1A input capture compare match TGI1B...

Page 136: ...width lower limit underflow TWDMXI0 Pulse width upper limit overflow TOVI0 Overflow 52 H 0000D0 TDP_1 TICI1 Input capture TCMI1 Compare match TPDMXI1 Cycle overflow TPDMNI1 Cycle underflow TWDMNI1 Pul...

Page 137: ...ICRB1 FSI FSII Transmission reception completion 79 H 00013C ICRC2 Reserved for system use Reserved for system use 80 81 H 000140 H 000144 SCIF SCIF SCIF interrupt 82 H 000148 ICRC7 Reserved for syste...

Page 138: ...ption completion D KBTID Transmission completion D KBCD 1st KCLKD 96 97 98 99 100 101 102 103 H 000180 H 000184 H 000188 H 00018C H 000190 H 000194 H 000198 H 00019C ICRB0 High FSI LFSII Command recep...

Page 139: ...WDT_1 WOVI1 Interval timer 26 H 000068 ICRA0 Address break 27 H 00006C A D converter ADI A D conversion end 28 H 000070 ICRB7 Reserved for system use 29 H 000074 External pin KIN7 to KIN0 KIN15 to KI...

Page 140: ...mpare match TOVMI1 Cycle overflow TUDI1 Cycle underflow TOVI1 Overflow 49 H 0000C4 TCM_2 TICI2 Input capture TCMI2 Compare match TOVMI2 Cycle overflow TUDI2 Cycle underflow TOVI2 Overflow 50 H 0000C8...

Page 141: ...erflow 64 65 66 H 000100 H 000104 H 000108 ICRB3 Reserved for system use 67 H 00010C TMR_1 CMIA1 Compare match A CMIB1 Compare match B OVI1 Overflow 68 69 70 H 000110 H 000114 H 000118 ICRB2 Reserved...

Page 142: ...n 95 H 00017C ICRC3 PS2 KBIA Reception completion A KBIB Reception completion B KBIC Reception completion C KBTIA Transmission completion A KBCA 1st KCLKA KBTIB Transmission completion B KBCB 1st KCLK...

Page 143: ...errupt control modes Table 5 7 Interrupt Control Modes SYSCR Interrupt Control Mode INTM1 INTM0 Priority Setting Registers Interrupt Mask Bits Description 0 0 0 ICR I Interrupt mask control is perform...

Page 144: ...l interrupts interrupt control level 1 has priority 0 1 NMI and address break interrupts 0 All interrupts interrupt control level 1 has priority 1 0 NMI address break and interrupt control level 1 int...

Page 145: ...the interrupt control level specified in ICR the interrupt controller only accepts an interrupt request with interrupt control level 1 priority and holds pending an interrupt request with interrupt co...

Page 146: ...ted by the contents of the vector address in the vector table Program execution state Interrupt generated NMI An interrupt with interrupt control level 1 IRQ0 IRQ1 IBFI3 IRQ0 IRQ1 IBFI3 I 0 Save PC an...

Page 147: ...interrupt enable bit corresponding to each interrupt is set to 1 and ICRA to ICRD are set to H 20 H 00 H 00 and H 00 respectively IRQ2 and IRQ3 interrupts are set to interrupt control level 1 and oth...

Page 148: ...when the I bit is set to 1 while the UI bit is cleared to 0 An interrupt request with interrupt control level 0 is accepted when the I bit is cleared to 0 When both the I and UI bits are set to 1 only...

Page 149: ...upt with interrupt control level 1 IRQ0 IRQ1 IBFI3 IRQ0 IRQ1 IBFI3 UI 0 Save PC and CCR I 1 UI 1 Read vector address Branch to interrupt handling routine Yes No Yes Yes Yes No No Yes No Yes No Yes Yes...

Page 150: ...ssing Internal processing Interrupt is accepted Interrupt level determination and wait for end of instruction Interrupt request signal Internal address bus Internal read signal Internal write signal I...

Page 151: ...tion Status Advanced Mode 1 Interrupt priority determination 1 3 2 Number of wait states until executing instruction ends 2 1 to 21 3 Saving of PC and CCR in stack 2 4 Vector fetch 2 5 Instruction fet...

Page 152: ...address break interrupt is generated address break interrupt exception handling is executed This function can be used to detect the beginning of execution of a bug location in the program and branch t...

Page 153: ...n interrupt is requested If necessary the source should be identified in the interrupt handling routine 5 7 4 Usage Notes With the address break function the address at which the first instruction byt...

Page 154: ...H 0316 NOP Program area in on chip memory 1 state execution instruction at specified break address Address bus Break request signal Program area in on chip memory 2 state execution instruction at spe...

Page 155: ...that interrupt will be executed on completion of the instruction However if there is an interrupt request of higher priority than that interrupt interrupt exception handling will be executed for the...

Page 156: ...transfer is completed With the EEPMOV W instruction if an interrupt request is issued during data transfer interrupt exception handling starts at a break in the transfer cycles The PC value saved on t...

Page 157: ...left floating When the external interrupt pins IRQ7 IRQ6 ExIRQ15 to ExIRQ8 KIN7 to KIN0 and WUE15 to WUE8 are used in software standby and watch modes the noise canceller should be disabled 5 8 6 Nois...

Page 158: ...Section 5 Interrupt Controller Rev 1 00 Apr 28 2008 Page 132 of 994 REJ09B0452 0100...

Page 159: ...R W Initial Value Address Data Bus Width Bus control register BCR R W H D3 H FFC6 8 Wait state control register WSCR R W H F3 H FFC7 8 6 1 1 Bus Control Register BCR Bit Bit Name Initial Value R W Des...

Page 160: ...1 R W Reserved The initial value should not be changed 5 ABW 1 R W Bus Width Control The initial value should not be changed 4 AST 1 R W Access State Control The initial value should not be changed 3...

Page 161: ...er DR that stores output data and a port input data register PIN used to read the pin states Port E does not have a DR or a DDR register Ports 1 to 3 6 9 B to D F H and J have internal input pull up M...

Page 162: ...LED Drive Capability 5 mA Sink Current On Chip Noise Canceler 7 P17 6 P16 5 P15 4 P14 3 P13 2 P12 1 P11 Port 1 General I O port 0 P10 O O 7 P27 6 P26 5 P25 4 P24 3 P23 2 P22 1 P21 Port 2 General I O p...

Page 163: ...B 3 P43 SCK2 TMI1 TCMCKI1 TCMMCI1 2 P42 SDA1 TCMCYI1 1 P41 RxD2 TCMCKI0 TCMMCI0 TMO0 Port 4 General I O port also functioning as PWMX and PWMU_B outputs TCM input and TMR_0 TMR_1 IIC_1 and SCI_2 input...

Page 164: ...input port also functioning as A D converter analog input 0 P70 AN0 6 P86 SCK1 SCL1 IRQ5 5 P85 RxD1 IRQ4 4 P84 IRQ3 TxD1 3 P83 LPCPD 2 P82 CLKRUN 1 P81 GA20 Port 8 General I O port also functioning as...

Page 165: ...O port also functioning as keyboard input and PS2 input output 0 PA0 PS2DC KIN8 7 PB7 RTS FSISS 6 PB6 CTS FSICK 5 PB5 FSIDI DTR 4 PB4 DSR FSIDO 3 PB3 DCD PWMU1B 2 PB2 RI PWMU0B 1 PB1 LSCI Port B Gener...

Page 166: ...ort D General I O port also functioning as A D converter analog input 0 PD0 AN8 O O 4 PE4 1 ETMS 3 PE3 1 ETDO 2 PE2 1 ETDI 1 PE1 1 ETCK Port E General input port also functioning as external sub clock...

Page 167: ...AA ExIRQ12 3 PG3 SCL2 ExIRQ11 2 PG2 SDA2 ExIRQ10 1 PG1 TMIY1 TDPCKI1 TDPMCI1 ExIRQ9 Port G General I O port also functioning as interrupt and TDP inputs TMR_X and TMR_Y inputs and IIC0 to IIC2 inputs...

Page 168: ...t I O Input Output Input Pull up MOS Function LED Drive Capability 5 mA Sink Current On Chip Noise Canceler 7 PJ7 2 6 PJ6 2 5 PJ5 2 4 PJ4 2 3 PJ3 2 2 PJ2 2 1 PJ1 2 Port J General I O port 0 PJ0 2 O No...

Page 169: ...O Port 3 8 O O O 2 O Port 4 8 O O O 2 Port 5 3 O O O 2 Port 6 8 O O O 2 O O O O Port 7 8 O Port 8 7 O O O 2 Port 9 8 O O O 2 O Port A 8 O O O Port B 8 O O O 2 O Port C 8 O O O 2 O O O O O Port D 8 O O...

Page 170: ...0 W 5 Pn5DDR 0 W 4 Pn4DDR 0 W 3 Pn3DDR 0 W 2 Pn2DDR 0 W 1 Pn1DDR 0 W 0 Pn0DDR 0 W The corresponding pins act as output ports when these bits are set to 1 and act as input ports when cleared to 0 Note...

Page 171: ...out the current settings of these bits for pins corresponding to PnDDR bits set to 1 and reads out the states of pins corresponding to PnDDR bits cleared to 0 7 1 3 Input Data Register PnPIN n 1 to 9...

Page 172: ...up MOS corresponding to the bit in PCR is turned on Table 7 3 shows the input pull up MOS state The upper two bits in P9PCR and the upper two bits in PHPCR are reserved PBPCR to PDPCR PFPCR and PHPCR...

Page 173: ...peration Port output Off Port 1 Port input Off On Off Port output Off Port 2 Port input Off On Off Port output Off Port 3 Port input Off On Off Port output Off Port 6 KMPCR Port input Off On Off Port...

Page 174: ...put Off On Off Port output Off Port C Port input Off On Off Port output Off Port D Port input Off On Off Port output Off Port F Port input Off On Off Port output Off Port H Port input Off On Off Legen...

Page 175: ...R W 0 Pn0ODR 0 R W ODR stores the output data for the pins that are used as the general output port 7 1 6 Noise Canceler Enable Register PnNCE n 6 C and G NCE enables or disables the noise cancel cir...

Page 176: ...the port data register when 1 is input stably 0 expected 0 is stored in the port data register when 0 is input stably 7 1 8 Noise Cancel Cycle Setting Register PnNCCS n 6 C and G NCCS controls the sam...

Page 177: ...Sampling clock selection Latch Pin input Latch Latch Matching detection circuit Latch 2 32 8192 16384 32768 65536 131072 262144 t t Figure 7 1 Noise Cancel Circuit P6n input PCn input PGn input n 7 t...

Page 178: ...the pins of port n that is specified as output The upper two bits in PHNOCR are reserved Bit Bit Name Initial Value R W Description 7 Pn7NOCR 0 R W 6 Pn6NOCR 0 R W 5 Pn5NOCR 0 R W 4 Pn4NOCR 0 R W 3 P...

Page 179: ...t in PTCNT2 Ports B to D F and H 1 PORTS 0 DDR 0 1 NOCR 0 1 ODR 0 1 0 1 0 1 N ch driver Off On Off On Off P ch driver Off Off On Off Input pull up MOS Off On Off Pin function Input pin Output pin 2 PO...

Page 180: ...port output signal s valid setting For details on the corresponding output signals see the register description of each peripheral module 7 2 1 Port 1 1 P17 to P10 The pin function is switched as sho...

Page 181: ...lowing table is expressed by the following logical expression LPCENABLE 1 FSILIE SCIFE LPC4E LPC3E LPC2E LPC1E Setting Logical expression I O Port Module Name Pin Function LPCENABLE P3nDDR LPC LPC out...

Page 182: ...I O Port Module Name Pin Function PWX0_OE PWMU4B_OE P46DDR PWMX PWX0 output 1 PWMU PWMU4B output 0 1 1 P46 output 0 0 1 I O port P46 input initial setting 0 0 3 P45 PWMU3B TCMCKI2 TCMMCI2 The pin func...

Page 183: ...O Port Module Name Pin Function TMO1_OE PWMU2B_OE P44DDR TMR TMO1 output 1 PWMU PWMU2B output 0 1 1 P44 output 0 0 1 I O port P44 input initial setting 0 0 5 P43 TMI1 SCK2 TCMCKI1 TCMMCI1 The pin func...

Page 184: ...42 input initial setting 0 0 Note To use this pin as SDA1 clear the IIC1AS and IIC1BS bits in PTCNT1 to 0 The output format for SDA1 is NMOS output only and direct bus drive is possible When this pin...

Page 185: ...5 Port 5 1 P52 SCL0 The pin function is switched as shown below according to the combination of the IIC0AS and IIC0BS bits in PTCNT1 ICE bit in ICCR of IIC_0 and the P52DDR bit Setting IIC_0 I O Port...

Page 186: ...Logical Expression I O Port Module Name Pin Function SCIFENABLE P51DDR SCIF FRxD input 1 P51 output 0 1 I O port P51 input initial setting 0 0 3 P50 FTxD The pin function is switched as shown below a...

Page 187: ...w according to the state of the P67DDR bit Setting I O Port Module Name Pin Function P67DDR P67 output 1 I O port P67 input initial setting 0 2 P66 KIN6 IRQ6 When the KMIM6 bit in KMIMR of the interru...

Page 188: ...leared to 0 this pin can be used as the KINn input pin The pin function is switched as shown below according to the state of the P6nDDR bit Setting I O Port Module Name Pin Function P6nDDR P6n output...

Page 189: ...in Function SCK1_OE SCL1_OE P86DDR SCI SCK1 input output 1 0 IIC SCL1 input output 0 1 P86 output 0 0 1 I O port P86 input initial setting 0 0 0 Note To use this pin as SCL1 input output be sure that...

Page 190: ...initial setting 0 0 4 P83 LPCPD The pin function is switched as shown below according to the combination of the FSILIE bit in SLCR of FSI the SCIFE bit in HICR5 and the LPC4E bit in HICR4 of the LPC...

Page 191: ...table is expressed by the following logical expression LPCENABLE 1 FSILIE SCIFE LPC4E LPC3E LPC2E LPC1E Setting Logical Expression I O Port Module Name Pin Function LPCENABLE P82DDR LPC CLKRUN output...

Page 192: ...combination of the IIC0AS and IIC0BS bits in PTCNT1 ICE bit in ICCR of IIC_0 and the P97DDR bit When the ISS15 bit in ISSR16 is cleared to 0 and the IRQ15E bit in IER16 of the interrupt controller is...

Page 193: ...96DDR Clock output 1 I O port P96 input initial setting 0 3 P95 IRQ14 P94 IRQ13 P93 IRQ12 P92 IRQ0 P91 IRQ1 P90 IRQ2 The pin function is switched as shown below according to the state of the P9nDDR bi...

Page 194: ...bit When the KMIMRm bit in KMIMRA of the interrupt controller is cleared to 0 this pin can be used as the KINm input pin Setting PS2 I O Port Module Name Pin Function PS2_OE PAnDDR PS2 PS2 input outp...

Page 195: ...the PB7DDR bit Setting FSI SCIF I O Port Module Name Pin Function FSISS_OE RTS_OE PB7DDR FSI FSISS output 1 SCIF RTS output 0 1 PB7 output 0 0 1 I O port PB7 input initial setting 0 0 0 2 PB6 CTS FSIC...

Page 196: ...it Setting FSI SCIF I O Port Module Name Pin Function FSIDI DTR_OE PB5DDR FSI FSIDI input 1 SCIF DTR output 0 1 PB5 output 0 0 1 I O port PB5 input initial setting 0 0 0 4 PB4 DSR FSIDO The pin functi...

Page 197: ...tting PWMU I O Port Module Name Pin Function PWMU1B_OE PB3DDR PWMU PWMU1B output 1 1 PB3 output 0 1 I O port PB3 input initial setting 0 6 PB2 RI PWMU0B The pin function is switched as shown below acc...

Page 198: ...bit Setting LPC I O Port Module Name Pin Function LSCI_OE PB1DDR LPC LSCI output 1 PB1 output 0 1 I O port PB1 input initial setting 0 0 8 PB0 LSMI The pin function is switched as shown below accordin...

Page 199: ...ating mode is set to normal operation or phase counting mode and IOB3 in TIOR_2 is set to 1 Setting TPU I O Port Module Name Pin Function TIOCB2_OE PC7DDR TPU TIOCB2 output 1 PC7 output 0 1 I O port P...

Page 200: ...ounting mode and IOB3 to IOB0 in TIOR_1 are set to B 10xx x Don t care Setting TPU I O Port Module Name Pin Function TIOCB1_OE PC5DDR TPU TIOCB1 output 1 PC5 output 0 1 I O port PC5 input initial sett...

Page 201: ...Setting TPU I O Port Module Name Pin Function TIOCD0_OE PC3DDR TPU TIOCD0 output 1 PC3 output 0 1 I O port PC3 input initial setting 0 0 6 PC2 WUE10 TIOCC0 TCLKA The pin function is switched as shown...

Page 202: ...Setting TPU I O Port Module Name Pin Function TIOCB0_OE PC1DDR TPU TIOCB0 output 1 PC1 output 0 1 I O port PC1 input initial setting 0 0 8 PC0 WUE8 TIOCA0 The pin function is switched as shown below a...

Page 203: ...et the pin as output Setting I O Port Module Name Pin Function PDnDDR PDn output 1 I O port PDn input initial setting 0 n 7 to 0 7 2 14 Port E 1 PE4 ETMS PE3 ETDO PE2 ETDI PE1 ETCK The pin function is...

Page 204: ...this pin can be used as the ExEXCL input pin Setting I O Port Module Name Pin Function ExEXCL I O port PE0 input initial setting 0 7 2 15 Port F 1 PF7 PWMU5 APF6 PWMU4A PF5 PWMU3A PF4 PWMU2A The pin f...

Page 205: ...bit in IER16 of the interrupt controller is set to 1 this pin can be used as the IRQ11 input pin Setting TMR I O Port Module Name Pin Function TMOX_OE PF3DDR TMR TMOX output 1 I O port PF3 output 0 1...

Page 206: ...tting PWMU I O Port Module Name Pin Function PWMU1A_OE PF1DDR PWMU PWMU1A output 1 1 PF1 output 0 1 I O port PF1 input initial setting 0 5 PF0 IRQ8 PWMU0A The pin function is switched as shown below a...

Page 207: ...for ExSCLB is NMOS output only and direct bus drive is possible When this pin is used as the PG7 output pin the output format is NMOS push pull 2 PG6 ExSDAB ExIRQ14 The pin function is switched as sho...

Page 208: ...CLA is NMOS output only and direct bus drive is possible When this pin is used as the PG5 output pin the output format is NMOS push pull 4 PG4 ExSDAA ExIRQ12 The pin function is switched as shown belo...

Page 209: ...CL2 is NMOS output only and direct bus drive is possible When this pin is used as the PG3 output pin the output format is NMOS push pull 6 PG2 SDA2 ExIRQ10 The pin function is switched as shown below...

Page 210: ...ISSR16 is set to 1 and the IRQ9E bit in IER16 of the interrupt controller is set to 1 this pin can be used as the ExIRQ9 input pin Setting I O Port Module Name Pin Function PG1DDR PG1 output 1 I O po...

Page 211: ...DDR bit Setting I O Port Module Name Pin Function PHnDDR PHn output 1 I O port PHn input initial setting 0 n 5 to 3 2 PH2 CIRI The pin function is switched as shown below according to the combination...

Page 212: ...in ISSR is set to 1 and the IRQ7E bit in IER of the interrupt controller is set to 1 this pin can be used as the ExIRQ7 input pin Setting I O Port Module Name Pin Function PH1DDR PH1 output 1 I O por...

Page 213: ...bit Setting I O Port Module Name Pin Function PInDDR PIn output 1 I O port PIn input initial setting 0 n 7 to 0 Note The output format for PIn is NMOS push pull 7 2 19 Port J 1 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2...

Page 214: ...ngs 7 P17_OE P17 6 P16_OE P16 5 P15_OE P15 4 P14_OE P14 3 P13_OE P13 2 P12_OE P12 1 P11_OE P11 P1 0 P10_OE P10 7 P27_OE P27 6 P26_OE P26 5 P25_OE P25 4 P24_OE P24 3 P23_OE P23 2 P22_OE P22 1 P21_OE P2...

Page 215: ...PWMCONB PWM3E 1 TMO1_OE TMO1 Except TMR_1 TCSR OS 3 0 0000 4 PWMU2B_OE PWMU2B PWMU_B PWMCONB PWM2E 1 3 SCK2_OE SCK2 SCI_2 SCR CKE 1 0 01 10 11 SMR C A 1 2 SDA1_OE SDA1 PTCNT1 IIC1AS PTCNT1 IIC1BS ICE...

Page 216: ...IE LPC HICR5 SCIFE HICR4 LPC4E HICR0 LPC 3E 1E LPCENABLE 1 FSILIE SCIFE LPC4E LPC3E LPC2E LPC1E 1 GA20_OE GA20 LPC HICR0 FGA20E 1 P8 0 PME_OE PME LPC HICR0 PMEE 1 7 SDA0_OE SDA PTCNT1 IIC0AS PTCNT1 II...

Page 217: ...FSICR1 FSIE 1 3 PWMU1B_OE PWMU1B PWMU_B PWMCONB PWM1E 1 2 PWMU0B_OE PWMU0B PWMU_B PWMCONB PWM0E 1 1 LSCI_OE LSCI LPC HICR0 LSCIE 1 PB 0 LSMI_OE LSMI LPC HICR0 LSMIE 1 7 TIOCB2_OE TIOCB2 TPU TIOR2 IOB3...

Page 218: ...3E 1 4 PWMU2A_OE PWMU2A PWMU_A PWMCONB PWM2E 1 3 TMOX_OE TMOX Except TMR_X TCSR OS 3 0 0000 2 TMOY_OE TMOY Except TMR_Y TCSR OS 3 0 0000 1 PWMU1A_OE PWMU1A PWMU_A PWMCONB PWM1E 1 PF 0 PWMU0A_OE PWMU0A...

Page 219: ...nal Name Output Signal Name Signal Selection Register Settings Internal Module Settings 7 PI7_OE PI7 6 PI6_OE PI6 5 PI5_OE PI5 4 PI4_OE PI4 3 PI3_OE PI3 2 PI2_OE PI2 1 PI1_OE PI1 PI 0 PI0_OE PI0 7 PJ7...

Page 220: ...nge the setting of PTCNT1 The pin name of the peripheral function is indicated by adding Ex at the head of the original pin name In each peripheral function description the original pin name is used T...

Page 221: ...P42 SDA1 0 1 Selects PG5 ExSCLA and PG4 ExSDAA 1 0 Selects PG7 ExSCLB and PG6 ExSDAB 1 1 Setting prohibited 4 5 0 0 R W Reserved The initial value should not be changed 3 2 IIC0BS IIC0AS 0 0 R W R W T...

Page 222: ...eserved The initial value should not be changed 6 TxD2RS 0 R W 0 TxD2 direct output 1 TxD2 inverted output 5 RxD2RS 0 R W 0 RxD2 direct input 1 RxD2 inverted input 4 TxD1RS 0 R W 0 TxD1 direct output...

Page 223: ...1 higher order and channel 0 lower order as a 16 bit single pulse PWM timer Operation of channel 3 higher order and channel 2 lower order as a 16 bit single pulse PWM timer Operation of channel 5 high...

Page 224: ...latch register Duty setting latch register PWM output waveform PWM output enable signal PWM control register A for clock control PWM control register B for output control PWM control register C for mo...

Page 225: ...pulse 8 bit pulse division 4 PWMU4A Output PWM pulse output 8 bit single pulse 8 bit pulse division Channel A 5 PWMU5A Output PWM pulse output 8 bit single pulse 16 bit single pulse 8 bit pulse divis...

Page 226: ...MCOND_A R W H 00 H FD0F 8 PWM prescaler register 0_A PWMPRE0_A R W H 00 H FD01 8 PWM prescaler register 1_A PWMPRE1_A R W H 00 H FD03 8 PWM prescaler register 2_A PWMPRE2_A R W H 00 H FD05 8 PWM presc...

Page 227: ...0_B PWMPRE0_B R W H 00 H FD11 8 PWM prescaler register 1_B PWMPRE1_B R W H 00 H FD13 8 PWM prescaler register 2_B PWMPRE2_B R W H 00 H FD15 8 PWM prescaler register 3_B PWMPRE3_B R W H 00 H FD17 8 PW...

Page 228: ...l clock 2 is selected 1 0 Internal clock 4 is selected 1 1 Internal clock 8 is selected 5 to 0 All 0 R Reserved These bits are always read as 0 and cannot be modified 8 3 2 PWM Control Register B PWMC...

Page 229: ...counter operation are enabled 3 PWM3E 0 R W PWMU3 Output Enable 0 PWMU3 output and counter operation are disabled 1 PWMU3 output and counter operation are enabled 2 PWM2E 0 R W PWMU2 Output Enable 8...

Page 230: ...R W Description 0 PWM0E 0 R W PWMU0 Output Enable 8 bit single pulse pulse division mode 0 PWMU0 output and counter operation are disabled 1 PWMU0 output and counter operation are enabled 16 bit singl...

Page 231: ...ify single pulse mode 5 PWMSL5 0 R W Channel 5 Operating Mode Select 0 Single pulse mode 1 Pulse division mode Specify 8 bit counter mode 4 PWMSL4 0 R W Channel 4 Operating Mode Select 0 Single pulse...

Page 232: ...hase Select 0 PWMU2 direct output 1 PWMU2 inverted output 3 PH1S 0 R W Channel 1 Output Phase Select 0 PWMU1 direct output 1 PWMU1 inverted output 2 PH0S 0 R W Channel 0 Output Phase Select 0 PWMU0 di...

Page 233: ...le is calculated as follows 1 8 Bit Single Pulse Mode PWM cycle 255 n 1 internal clock frequency 0 n 255 Table 8 3 Resolution PWM Conversion Period and Carrier Frequency 8 Bit Counter Operation when 2...

Page 234: ...olution Min Max Min Max 50 ns 3 3 ms 838 9 ms 1 2 Hz 305 1 Hz 2 100 ns 6 5 ms 1 7 s 0 6 Hz 152 6 Hz 4 200 ns 13 1 ms 3 4 s 0 3 Hz 76 3 Hz 8 400 ns 26 2 ms 6 7 s 0 15 Hz 38 1 Hz 3 8 Bit Pulse Division...

Page 235: ...r PWM output With cascade connected PWMREG registers the duty cycle of the PWM output pulse is specified as a value from 0 65535 to 65535 65535 When the PWMREG value is m the high period of the output...

Page 236: ...gle pulse mode or 8 bit division pulse mode 8 4 1 Single Pulse Mode 8 Bits 16 Bits Figure 8 2 shows a block diagram of 8 bit single pulse mode Figure 8 3 shows a block diagram of 16 bit single pulse m...

Page 237: ...PWMU Rev 1 00 Apr 28 2008 Page 211 of 994 REJ09B0452 0100 Clock generator PRELAT0 CNT0 REGLAT0 Comparator 0 PWMU00 Output disabled PRELAT1 CNT1 REGLAT1 Comparator 1 PWMU01 Figure 8 3 Block Diagram of...

Page 238: ...y counter is incremented When the clock generator counter is H 00 the PWM clock is generated by decrementing the PRELAT value Figure 8 4 shows an example of duty counter and clock generator counter op...

Page 239: ...counter REGLAT REGLAT value after write H 00 PWMUO PWMREG write signal Figure 8 6 PWMU Output Waveform When PWMREG Value is Changed When the PWMPRE value is changed during PWM output the PWM cycle cha...

Page 240: ...specify the duty cycle of the basic pulse as 0 16 to 15 16 with a resolution of 1 16 The following shows the duty cycle of the basic pulse Table 8 6 Basic Pulse Duty Cycle 0 1 2 3 4 5 6 7 8 9 A B C D...

Page 241: ...basic pulses and figure 8 8 shows an example of additional pulse timing Table 8 7 Additional Pulse Positions Corresponding to Basic Pulse Basic Pulse Number Lower 4 Bits 0 1 2 3 4 5 6 7 8 9 10 11 12...

Page 242: ...example H 7F H 80 H 81 H 82 112 pulses 128 pulses 128 pulses 128 pulses 15 pulses 0 pulse 1 pulse 2 pulses Figure 8 9 Example of WMU Setting 2 Example of Circuit for Use as D A Converter The followin...

Page 243: ...Timer When the duty cycle is to be changed in usage of a 16 bit single pulse PWM timer the higher and lower order eight bits must be individually written to the respective PWMREGn n 0 to 5 registers T...

Page 244: ...Section 8 8 Bit PWM Timer PWMU Rev 1 00 Apr 28 2008 Page 218 of 994 REJ09B0452 0100...

Page 245: ...r T 256 where T is the resolution Sixteen operation clocks by combination of eight resolution settings and two base cycle settings Figure 9 1 shows a block diagram of the PWM D A module Select clock P...

Page 246: ...ection 26 1 3 Module Stop Control Registers H L A and B MSTPCRH MSTPCRL MSTPCRA MSTPCRB Table 9 2 Register Configuration Register Name Abbreviation R W Initial Value Address Data Bus Width PWMX D A co...

Page 247: ...ween the CPU is performed through the temporary register TEMP For details see section 9 4 Bus Master Interface 7 6 5 4 3 2 1 0 8 9 10 11 12 13 15 Bit counter Bit CPU 14 DACNTH DACNTL 13 12 11 10 9 8 7...

Page 248: ...t a digital value to be converted to an analog value In each base cycle the DACNT value is continually compared with the DADR value to determine the duty cycle of the output waveform and to decide whe...

Page 249: ...t a fine adjustment pulse equal in width to the resolution To enable this operation this register must be set within a range that depends on the CFS bit If the DADR value is outside this range the PWM...

Page 250: ...r disables output on PWMX D A channel B 0 PWMX D A channel B output at the PWX1 output pin is disabled 1 PWMX D A channel B output at the PWX1 output pin is enabled 2 OEA 0 R W Output Enable A Enables...

Page 251: ...All 0 R W Reserved The initial value should not be changed 0 PWCKXC 0 R W PWMX clock select This bit selects a clock cycle with the CKS bit of DACR of PWMX being 1 See table 9 3 Table 9 3 Clock Selec...

Page 252: ...lue are combined and the combined 16 bit value is written in the register Read When the upper byte is read from the upper byte value is transferred to the CPU and the lower byte value is transferred t...

Page 253: ...ccess Word unit access includes accessing byte sequentially first upper byte and then lower byte The result of the access in the unit cannot be guaranteed a Write to upper byte CPU H AA Upper byte TEM...

Page 254: ...EJ09B0452 0100 a Read upper byte CPU H AA Upper byte TEMP H 57 DACNTH H AA DACNTL H 57 Bus interface Module data bus b Read lower byte CPU H 57 Lower byte TEMP H 57 DACNTH DACNTL Bus interface Module...

Page 255: ...o DA0 in DADR value corresponds to the total width TH of the high 1 output pulses Figures 9 4 and 9 5 show the types of waveform output available tf tL T Resolution TL tLn OS 0 When CFS 0 m 256 When C...

Page 256: ...utput DA13 to 0 H 0000 to H 00FF Data value T DA13 to 0 H 0100 to H 3FFF 10 0 0 0 0 102 4 s 1 25 6 14 1638 4 s s 12 0 0 409 6 s 2 39 1kHz Always low high output DA13 to 0 H 0000 to H 003F Data value T...

Page 257: ...FFF 10 0 0 0 0 52 4 ms 1 13 1 14 838 9 ms ms 12 0 0 209 7 ms 1024 76 3Hz Always low high output DA13 to 0 H 0000 to H 003F Data value T DA13 to 0 H 0040 to H 3FFF 10 0 0 0 0 52 4 ms 1 0 1 1 204 8 0 13...

Page 258: ...5 tL256 1 conversion cycle tf1 tf2 tf3 tf255 tf256 T 64 tL1 tL2 tL3 tL255 tL256 TL tf1 tf2 tf63 tf64 tL1 tL2 tL3 tL63 tL64 1 conversion cycle tf1 tf2 tf3 tf63 tf64 T 256 tL1 tL2 tL3 tL63 tL64 TL a CFS...

Page 259: ...ut Waveform OS 1 DADR corresponds to TH An example of the additional pulses when CFS 1 base cycle resolution T 256 and OS 1 inverted PWM output is described below When CFS 1 the upper eight bits DA13...

Page 260: ...ut only at the location of base pulse No 63 according to table 9 6 Thus an additional pulse of 1 256 T is to be added to the base pulse 1 conversion cycle Base pulse High width 2 256 T Base pulse 2 25...

Page 261: ...1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1...

Page 262: ...00 9 6 Usage Notes 9 6 1 Module Stop Mode Setting PWMX operation can be enabled or disabled by using the module stop control register In the initial state PWMX operation is disabled Register access is...

Page 263: ...el 1 The following operations can be set for each channel Waveform output at compare match Input capture function Counter clear operation Multiple timer counters TCNT can be written to simultaneously...

Page 264: ...ter Timer control register Timer mode register Timer I O control registers H L Timer interrupt enable register Timer status register TImer general registers A B C D TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1...

Page 265: ...TGR TGRA_0 TGRB_0 TGRA_1 TGRB_1 TGRA_2 TGRB_2 General registers buffer registers TGRC_0 TGRC_0 I O pins TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 Counter clear function TGR compare matc...

Page 266: ...RA_2 compare match or input capture Interrupt sources 5 sources Compare match or input capture 0A Compare match or input capture 0B Compare match or input capture 0C Compare match or input capture 0D...

Page 267: ...put pin Channel 2 phase counting mode B phase input TIOCA0 I O TGRA_0 input capture input output compare output PWM output pin TIOCB0 I O TGRB_0 input capture input output compare output PWM output pi...

Page 268: ...register B_0 TGRB_0 R W H FFFF H FE5A 16 Timer general register C_0 TGRC_0 R W H FFFF H FE5C 16 Channel 0 Timer general register D_0 TGRD_0 R W H FFFF H FE5E 16 Timer control register_1 TCR_1 R W H 0...

Page 269: ...0 R W R W R W Counter Clear 2 to 0 These bits select the TCNT counter clearing source See tables 10 4 and 10 5 for details 4 3 CKEG1 CKEG0 0 0 R W R W Clock Edge 1 and 0 These bits select the input cl...

Page 270: ...performing synchronous clearing synchronous operation 1 Notes 1 Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1 2 When TGRC or TGRD is used as a buffer register TCNT i...

Page 271: ...nal clock counts on TCLKB pin input 0 External clock counts on TCLKC pin input 0 1 1 1 External clock counts on TCLKD pin input Table 10 7 TPSC2 to TPSC0 channel 1 Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit...

Page 272: ...Description 0 Internal clock counts on 0 1 Internal clock counts on 4 0 Internal clock counts on 16 0 1 1 Internal clock counts on 64 0 External clock counts on TCLKA pin input 0 1 External clock coun...

Page 273: ...apture output compare is not generation Because channels 1 and 2 have no TGRD bit 5 is reserved It is always read as 0 and cannot be modified 0 TGRB operates normally 1 TGRB and TGRD used together for...

Page 274: ...rmal operation 0 1 Reserved 0 PWM mode 1 0 1 1 PWM mode 2 0 Phase counting mode 1 0 1 Phase counting mode 2 0 Phase counting mode 3 0 1 1 1 Phase counting mode 4 1 Setting prohibited Legend x Don t ca...

Page 275: ...hich the counter is cleared to 0 is specified When TGRC or TGRD is designated for buffer operation this setting is invalid and the register operates as a buffer register TIORH_0 TIOR_1 TIOR_2 Bit Bit...

Page 276: ...1 Initial output is 0 output Toggle output at compare match 0 Output disabled 0 1 Initial output is 1 output 0 output at compare match 0 Initial output is 1 output 1 output at compare match 0 1 1 1 O...

Page 277: ...1 Initial output is 0 output Toggle output at compare match 0 Output disabled 0 1 Initial output is 1 output 0 output at compare match 0 Initial output is 1 output 1 output at compare match 0 1 1 1 O...

Page 278: ...0 1 Initial output is 1 output 0 output at compare match 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output Compare register Initial output is 1 output Toggle output at compare matc...

Page 279: ...0 1 Initial output is 1 output 0 output at compare match 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare register Initial output is 1 output Toggle output at compare mat...

Page 280: ...1 Initial output is 0 output Toggle output at compare match 0 Output disabled 0 1 Initial output is 1 output 0 output at compare match 0 Initial output is 1 output 1 output at compare match 0 1 1 1 O...

Page 281: ...1 Initial output is 0 output Toggle output at compare match 0 Output disabled 0 1 Initial output is 1 output 0 output at compare match 0 Initial output is 1 output 1 output at compare match 0 1 1 1 O...

Page 282: ...e match 0 1 1 Initial output is 0 output Toggle output at compare match 0 Output disabled 0 1 Initial output is 1 output 0 output at compare match 0 Initial output is 1 output 1 output at compare matc...

Page 283: ...e match 0 1 1 Initial output is 0 output Toggle output at compare match 0 Output disabled 0 1 Initial output is 1 output 0 output at compare match 0 Initial output is 1 output 1 output at compare matc...

Page 284: ...e modified 5 TCIEU 0 R W Underflow Interrupt Enable Enables or disables interrupt requests TCIU by the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1 and 2 In channel 0 bit 5 is reserve...

Page 285: ...nd cannot be modified 0 Interrupt requests TGIC by TGFC disabled 1 Interrupt requests TGIC by TGFC enabled 1 TGIEB 0 R W TGR Interrupt Enable B Enables or disables interrupt requests TGIB by the TGFB...

Page 286: ...wn 1 TCNT counts up 6 1 R Reserved This bit is always read as 1 and cannot be modified 5 TCFU 0 R W Underflow Flag Status flag that indicates that TCNT underflow has occurred when channels 1 and 2 are...

Page 287: ...is transferred to TGRD by input capture signal while TGRD is functioning as input capture register Clearing condition When 0 is written to TGFD after reading TGFD 1 2 TGFC 0 R W Input Capture Output...

Page 288: ...TGRB is functioning as input capture register Clearing condition When 0 is written to TGFB after reading TGFB 1 0 TGFA 0 R W Input Capture Output Compare Flag A Status flag that indicates the occurren...

Page 289: ...be accessed as a 16 bit unit TGR buffer register combinations are TGRA TGRC and TGRB TGRD 10 3 8 Timer Start Register TSTR TSTR is an 8 bit readable writable register that selects operation stoppage f...

Page 290: ...0 These bits select whether operation is independent of or synchronized with other channels When synchronous operation is selected synchronous presetting of multiple channels and synchronous clearing...

Page 291: ...16 bit access must always be used An example of 16 bit register access operation is shown in figure 10 2 H L TCNTH TCNTL Internal data bus Bus interface Module data bus Bus master Figure 10 2 16 Bit R...

Page 292: ...igure 10 3 8 Bit Register Access Operation Bus Master TCR Upper 8 Bits H L TMDR Internal data bus Bus interface Module data bus Bus master Figure 10 4 8 Bit Register Access Operation Bus Master TMDR L...

Page 293: ...6 shows an example of the count operation setting procedure Operation selection Select counter clock Periodic counter Select counter clearing source Select output compare register Set period Free run...

Page 294: ...tion TCNT value H FFFF H 0000 CST bit TCFV Time Figure 10 7 Free Running Counter Operation When compare match is selected as the TCNT clearing source the TCNT counter for the relevant channel performs...

Page 295: ...ut by compare match Figure 10 9 shows an example of the setting procedure for waveform output by compare match Output selection Select waveform output mode Set output timing Start count operation Wave...

Page 296: ...evel does not change TCNT value H FFFF H 0000 TIOCA TIOCB Time TGRA TGRB No change No change No change No change 1 output 0 output Figure 10 10 Example of 0 Output 1 Output Operation Figure 10 11 show...

Page 297: ...put capture operation setting procedure Figure 10 12 shows an example of the input capture operation setting procedure Input selection Select input capture input Start count Input capture operation De...

Page 298: ...nd falling edges have been selected as the TIOCA pin input capture input edge falling edge has been selected as the TIOCB pin input capture input edge and counter clearing by TGRB input capture has be...

Page 299: ...synchronous operation Synchronous presetting Set TCNT Synchronous presetting Counter clearing Synchronous clearing Synchronous clearing Clearing source generation channel Select counter clearing sour...

Page 300: ...learing has been set for the channel 1 and 2 counter clearing source Three phase PWM waveforms are output from pins TIOC0A TIOC1A and TIOC2A At this time synchronous presetting and synchronous clearin...

Page 301: ..._0 TGRC_0 TGRB_0 TGRD_0 When TGR is an output compare register When a compare match occurs the value in the buffer register for the corresponding channel is transferred to the timer general register T...

Page 302: ...ation setting procedure Buffer operation Select TGR function Set buffer operation Start count Buffer operation 1 2 3 1 2 3 Designate TGR as an input capture register or output compare register by mean...

Page 303: ...e TCNT clearing by compare match B 1 output at compare match A and 0 output at compare match B As buffer operation has been set when compare match A occurs the output changes and the value in buffer r...

Page 304: ...and TGRC Counter clearing by TGRA input capture has been set for TCNT and both rising and falling edges have been selected as the TIOCA pin input capture input edge As buffer operation has been set w...

Page 305: ...the TIOCA and TIOCC pins at compare matches A and C and the output specified by bits IOB3 to IOB0 and IOD3 to IOD0 in TIOR is output at compare matches B and D The initial output value is the value se...

Page 306: ...procedure PWM mode Select counter clock Select counter clearing source Select waveform output level Set TGR Set PWM mode Start count PWM mode Select the counter clock with bits TPSC2 to TPSC0 in TCR A...

Page 307: ...leared by TGRA compare match Figure 10 22 Example of PWM Mode Operation 1 Figure 10 23 shows an example of PWM mode 2 operation In this example synchronous operation is designated for channels 0 and 1...

Page 308: ...ten TGRB rewritten TCNT value TGRA H 0000 TIOCA Time TGRB 100 duty TGRB rewritten TGRB rewritten TGRB rewritten Output does not change when cycle register and duty register compare matches occur simul...

Page 309: ...rs while TCNT is counting up the TCFV flag in TSR is set when underflow occurs while TCNT is counting down the TCFU flag is set The TCFD bit in TSR is the count direction flag Reading the TCFD flag pr...

Page 310: ...ows an example of phase counting mode 1 operation and table 10 21 summarizes the TCNT up down count conditions TCNT value Time Down count Up count TCLKA channel 1 TCLKC channel 2 TCLKB channel 1 TCLKD...

Page 311: ...CNT value TCLKA channel 1 TCLKC channel 2 TCLKB channel 1 TCLKD channel 2 Figure 10 27 Example of Phase Counting Mode 2 Operation Table 10 22 Up Down Count Conditions in Phase Counting Mode 2 TCLKA Ch...

Page 312: ...CNT value TCLKA channel 1 TCLKC channel 2 TCLKB channel 1 TCLKD channel 2 Figure 10 28 Example of Phase Counting Mode 3 Operation Table 10 23 Up Down Count Conditions in Phase Counting Mode 3 TCLKA Ch...

Page 313: ...Up count Down count TCNT value TCLKA channel 1 TCLKC channel 2 TCLKB channel 1 TCLKD channel 2 Figure 10 29 Example of Phase Counting Mode 4 Operation Table 10 24 Up Down Count Conditions in Phase Co...

Page 314: ...by the interrupt controller but the priority order within a channel is fixed For details see section 5 Interrupt Controller Table 10 25 lists the TPU interrupt sources Table 10 25 TPU Interrupts Chann...

Page 315: ...low interrupts one for each channel 3 Underflow Interrupt An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a...

Page 316: ...count timing in internal clock operation and figure 10 31 shows TCNT count timing in external clock operation TCNT TCNT input clock Internal clock N 1 N N 1 N 2 Falling edge Rising edge Figure 10 30...

Page 317: ...e set in TIOR is output at the output compare output pin TIOC pin After a match between TCNT and TGR the compare match signal is not generated until the TCNT input clock is generated Figure 10 32 show...

Page 318: ...g when counter clearing by compare match occurrence is specified and figure 10 35 shows the timing when counter clearing by input capture occurrence is specified TCNT Counter clear signal Compare matc...

Page 319: ...Operation Timing Figures 10 36 and 10 37 show the timing in buffer operation TGRA TGRB Compare match signal TCNT TGRC TGRD n N N n n 1 Figure 10 36 Buffer Operation Timing Compare Match TGRA TGRB TCNT...

Page 320: ...rence and TGI interrupt request signal timing TGR TCNT TCNT input clock N N N 1 Compare match signal TGF flag TGI interrupt Figure 10 38 TGI Interrupt Timing Compare Match 2 TGF Flag Setting Timing in...

Page 321: ...V interrupt request signal timing Figure 10 41 shows the timing for setting of the TCFU flag in TSR by underflow occurrence and TCIU interrupt request signal timing Overflow signal TCNT overflow TCNT...

Page 322: ...g Clearing Timing After a status flag is read as 1 by the CPU it is cleared by writing 0 to it Figure 10 42 shows the timing for status flag clearing by the CPU T1 T2 TSR write cycle TSR address Addre...

Page 323: ...tes Figure 10 43 shows the input clock conditions in phase counting mode Overlap Phase differ ence Phase differ ence Overlap TCLKA TCLKC TCLKB TCLKD Pulse width Pulse width Pulse width Pulse width Not...

Page 324: ...nter clear signal Write signal Address TCNT address TCNT TCNT write cycle T1 T2 N H 0000 Figure 10 44 Conflict between TCNT Write and Clear Operations 10 8 4 Conflict between TCNT Write and Increment...

Page 325: ...f the same value as before is written Figure 10 46 shows the timing in this case Compare match signal Write signal Address TGR address TCNT TGR write cycle T1 T2 N M TGR write data TGR N N 1 Prohibite...

Page 326: ...lict between Buffer Register Write and Compare Match 10 8 7 Conflict between TGR Read and Input Capture If the input capture signal is generated in the T1 state of a TGR read cycle the data that is re...

Page 327: ...ot performed Figure 10 49 shows the timing in this case Input capture signal Write signal Address TCNT TGR write cycle T1 T2 M TGR M TGR address Figure 10 49 Conflict between TGR Write and Input Captu...

Page 328: ...nd Input Capture 10 8 10 Conflict between Overflow Underflow and Counter Clearing If overflow underflow and counter clearing occur simultaneously the TCFV TCFU flag in TSR is not set and TCNT clearing...

Page 329: ...M TCNT write data TCFV flag Figure 10 52 Conflict between TCNT Write and Overflow 10 8 12 Multiplexing of I O Pins In this LSI the TCLKA input pin is multiplexed with the TIOCC0 I O pin the TCLKB inp...

Page 330: ...Section 10 16 Bit Timer Pulse Unit TPU Rev 1 00 Apr 28 2008 Page 304 of 994 REJ09B0452 0100...

Page 331: ...a 16 bit counter that provides the basis for measuring the periods of input waveforms 11 1 Features Capable of measuring the periods of input waveforms Sensed edge is selectable 16 bit compare match 1...

Page 332: ...matrch Cycle upper limit overflow Cycle lower limit underflow Overflow Control logic Clear Input capture TCMIER TCMCR TICI TCMI TOVMI TUDI TOVI Legend TCMCNT TCMMLCM TCMMINCM TCMICR TCMICRF TCMCSR TC...

Page 333: ...rnal event input TCMCKI3 TCMMCI3 Input External counter clock input Cycle measurement control input 3 TCMCYI3 Input External event input 11 3 Register Descriptions The TCMs have the following register...

Page 334: ...16 TCM cycle upper limit register_2 TCMMLCM_2 R W H FFFF H FBE2 16 TCM cycle lower limit register_2 TCMMINCM_2 R W H 0000 H FBEC 16 TCM input capture register_2 TCMICR_2 R H 0000 H FBE4 16 TCM input...

Page 335: ...essed in 8 bit units TCMCNT is initialized to H 0000 11 3 2 TCM Cycle Upper Limit Register TCMMLCM TCMMLCM is a 16 bit readable writable register TCMMLCM is available as a compare match register when...

Page 336: ...in 16 bit units and cannot be accessed in 8 bit units TCMMINCM is initialized to H 0000 11 3 4 TCM Input Capture Register TCMICR TCMICR is a 16 bit read only register In timer mode the value in TCMCNT...

Page 337: ...of cycles of the waveform for measurement in cycle measurement mode has reached the upper limit set in TCMMLCM causing an overflow Setting condition A greater value for TCMICR than TCMMLCM Clearing co...

Page 338: ...IEDG bit in TCMCR during the measurement period Setting condition Generation of the input capture signal Clearing condition Reading ICPF when ICPF 1 and then writing 0 to ICPF 2 MINUDF 0 R W Measureme...

Page 339: ...0 and input capture operation stops Clear this bit and thus return TCMCNT to H 0000 in initialization for cycle measurement mode 6 POCTL 0 R W TCMCYI Input Polarity Reversal 0 Use the TCMCYI input dir...

Page 340: ...f the TCMCYI input 1 Selects the rising edge of the TCMCYI input 3 TCMMDS 0 R W TCM Mode Select Selects the TCM operating mode 0 Timer mode The TCM provides compare match and input capture facilities...

Page 341: ...f interrupt requests on setting of the MAXOVF flag in TCMCSR to 1 0 Disable interrupt requests by MAXOVF 1 Enable interrupt requests by MAXOVF 5 CMIE 0 R W Compare Match Interrupt Enable Enables or di...

Page 342: ...requests by MINUDF 1 Enable interrupt requests by MINUDF 1 CMMS 0 R W Cycle Measurement Mode Selection Selects use of the TCMMCI signal in cycle measurement mode 0 The TCMMCI signal is not used cycle...

Page 343: ...T overflows the value changes from H FFFF to H 0000 the OVF bit in TCMCSR is set to 1 and an interrupt request is generated if the OVIE bit in TCMIER is 1 Figure 11 2 shows an example of free running...

Page 344: ...of rising or falling edges is selectable with the setting of the IEDG bit in TCMCR Figure 11 4 shows an example of the timing of input capture operations and figure 11 5 shows buffer operation of inpu...

Page 345: ...ag is set TCMCNT TCMMLC CMF N 1 N N Compare match signal Figure 11 6 Timing of CMF Flag Setting on a Compare Match 11 4 2 Cycle Measurement Mode When the TCMMDS bit in TCMCR is set to 1 the TCM operat...

Page 346: ...TCMMINCM If TCMICR is larger than TCMMLCM the MAXOVF bit in TCMCSR is set to 1 If TCMICR is smaller than TCMMINCM the MINUDF bit in TCMCSR is set to 1 If generation of the corresponding interrupt req...

Page 347: ...External Event TCMCYI Stoppage The timer overflow flag can be used to determine the external event TCMCYI stopped state Either of two sets of conditions represents the external event stopped state The...

Page 348: ...ement In this case the external event can be considered to have stopped if a timer overflow is generated before detection of the first edge Figure 11 11 shows an example of the timing of the external...

Page 349: ...d Processing for external event stopped state Processing for cycle upper limit over End of exception handling Set TCMMDS 0 End of measurement OVF 1 or MAXOVF 1 MAXOVF 1 1 2 3 5 6 1 2 3 5 6 9 9 7 7 8 8...

Page 350: ...rces Channel Name Interrupt Source Interrupt Flag Priority TICI0 TCMICR_0 input capture ICPF_0 High TCMI0 TCMMLCM_0 compare match CMF_0 TOVMI0 TCMMLCM_0 overflow MAXOVF_0 TUDI0 TCMMINCM_0 underflow MI...

Page 351: ...Internal write signal Internal clock TCMCNT input clock T1 T2 TCMCNT N 1 N N 1 Figure 11 13 Conflict between TCMCNT Write and Count Up Operation 11 6 2 Conflict between TCMMLCM Write and Compare Matc...

Page 352: ...N 1 N M TCMCNT Figure 11 15 Conflict between TCMICR Read and Input Capture 11 6 4 Conflict between Edge Detection in Cycle Measurement Mode and Writing to TCMMLCM or TCMMINCM If the selected edge of T...

Page 353: ...ing of this conflict Internal write signal Input capture signal N 1 N H 0000 M N M L TCMCYI TCMCNT cleared at the first rising edge TCMCNT not cleared TCMCNT TCMICR TCMMDS Figure 11 17 Conflict betwee...

Page 354: ...Section 11 16 Bit Cycle Measurement Timer TCM Rev 1 00 Apr 28 2008 Page 328 of 994 REJ09B0452 0100...

Page 355: ...ring input waveforms and the pulse width 12 1 Features Capable of measuring input waveform periods and the pulse width Selectable measured edge 16 bit compare match 16 bit resolution Selectable counte...

Page 356: ...PWDMN Timer counter Cycle upper limit register Cycle lower limit register Pulse width upper limit register Pulse width lower limit register TDPICR TDPICRF TDPCSR TDPCR1 TDPCR2 TDPIER Input capture reg...

Page 357: ...riptions The TDP has the following registers Table 12 2 Register Configuration Channel Register Name Abbreviation R W Initial Value Address Data Bus Width TDP timer counter_0 TDPCNT_0 R W H 0000 H FB4...

Page 358: ...R W H 00 H FB6C 8 TDP control register1_1 TDPCR1_1 R W H 00 H FB6D 8 TDP control register2_1 TDPCR2_1 R W H 00 H FB6F 8 Channel 1 TDP interrupt enable register_1 TDPIER_1 R W H 00 H FB6E 8 TDP timer...

Page 359: ...nits TDPCNT is initialized to H 0000 12 3 2 TDP Pulse Width Upper Limit Register TDPWDMX TDPWDMX is a 16 bit readable writable register When the TDPMDS bit in TDPCR1 is cleared timer mode TDPWDMX is a...

Page 360: ...per limit register In cycle measurement mode TDPPDMX can be used to set the upper limit value of measurement period When the third edge the first edge of the next period of the measurement period is d...

Page 361: ...gister TDPICRF can be used as a TDPICR buffer register When input capture occurs the TDPICR value is transferred to TDPICRF TDPICRF must always be accessed in 16 bit units and cannot be accessed in 8...

Page 362: ...measurement mode has exceeded the upper limit specified in TDPPDMX Setting condition When TDPICR is greater than TDPPDMX Clearing condition Reading TPDMXOVF when TPDMXOVF 1 and then writing 0 to TPDMX...

Page 363: ...F is not set to 1 1 CKSEG 0 R W External Clock Edge Select When CKS2 to CKS0 in TDPCR1 are set to B 111 external clock this bit selects the edge for counting of the external count clock edges 0 Fallin...

Page 364: ...capture operation stops Clear this bit to initialize TDPCNT to H 0000 before setting to cycle measurement mode 6 POCTL 0 R W TDPCYI Input Polarity Inversion 0 TDPCYI input is used directly 1 TDPCYI in...

Page 365: ...ct Selects the TDP operating mode 0 Timer mode In timer mode the operating mode is input capture and compare match 1 Cycle measurement mode Setting this bit to 1 starts counting by TDPCNT Clear the CS...

Page 366: ...MCI signal in cycle measurement mode 0 The TDPMCI signal is not used cycle measurement is always performed 1 The TDPMCI signal is used cycle measurement is performed only while the TDPMCI signal is hi...

Page 367: ...ts are enabled 5 TWDMNIE 0 R W Pulse Width Lower Limit Underflow Interrupt Enable Enables or disables the issuing of TWDMNUDF interrupt requests when the TWDMNUDF flag in TDPCSR is set to 1 0 TWDMNUDF...

Page 368: ...o use input capture and cycle measurement mode set this bit to 1 0 Disabled 1 Enabled Note Change this bit when CST 0 and TDPMDS 0 0 TPDMNIE 0 R W Cycle Lower Limit Underflow Interrupt Enable Enables...

Page 369: ...to 1 When TDPCNT overflows H FFFF changes to H 0000 the OVF bit in TDPCSR is set to 1 and an interrupt request is generated if the OVIE bit in TDPIER is 1 Figure 12 2 shows an example of free running...

Page 370: ...ng or falling edges is selectable by setting the IEDG bit in TDPCR1 Figure 12 4 shows an example of the timing of input capture operations and figure 12 5 shows an example of buffer operation for inpu...

Page 371: ...are Match Figure 12 6 shows the timing on which the CMF flag is set TDPCNT TDPWDMX CMF N 1 N N Compare match signal Figure 12 6 Timing of CMF Flag Setting on Compare Match 12 4 2 Cycle Measurement Mod...

Page 372: ...value in TDPICR is compared with the values in TDPWDMX and TDPWDMN If TDPIR is greater than TDPWDMX or less than TDPWDMN the TWDMXOVF or TWDMNUDF flag respectively in TDPCSR is set to 1 When the third...

Page 373: ...DPWDMX TDPWDMN TDPPDMX TDPPDMN TDPICRF Figure 12 8 Example of Timing in Cycle Measurement When the PMMS bit in TDPCR2 is set to 1 cycle measurement is performed only while the TDPMCI signal is high Fi...

Page 374: ...H 0000 H FFFF H 0000 N H 0000 H 0001 H 0002 OVF Stoppage for an external event can be determined Figure 12 10 Example of Timing for Stoppage for an External Event 1 When any of the TWDMXOVF TWDMNUDF T...

Page 375: ...pped state Processing for exceeded upper limit of pulse width End of exception handling Set TDPMDS 0 End of measurement OVF 1 or TWDMXOVF 1 TWDMXOVF 1 1 2 3 Set TDPIPE 1 4 5 6 1 2 3 4 9 7 8 Set timer...

Page 376: ...I0 TDPWDMX_0 compare match CMF_0 TWDMXI0 TDPWDMX_0 overflow TWDMXOVF_0 TWDMNI0 TDPWDMN_0 underflow TWDMNUDF_0 TPDMXI0 TDPPDMX_0 overflow TPDMXOVF_0 TPDMNI0 TDPPDMN_0 underflow TPDMNUDF_0 TDP_0 TOVI0 T...

Page 377: ...onflict Internal write signal Write data M Internal clock TDPCNT input clock T1 T2 TDPCNT N 1 M M 1 Figure 12 13 Conflict between TDPCNT Write and Counting Up 12 6 2 Conflict between TDPPDMX Write and...

Page 378: ...between Input Capture and TDPICR Read 12 6 4 Conflict between Edge Detection in Cycle Measurement Mode and Writing to the Upper Limit or Lower Limit Register If the edge of TDPCYI is detected in the...

Page 379: ...1 N H 0000 M N M L TDPCYI TDPCNT cleared at the first rising edge TDPCNT is not cleared Input capture signal TDPCNT TDPICR Internal write signal TDPMDS Figure 12 17 Conflict between Edge Detection and...

Page 380: ...Section 12 16 Bit Duty Period Measurement Timer TDP Rev 1 00 Apr 28 2008 Page 354 of 994 REJ09B0452 0100...

Page 381: ...compare match signals The timer output signal in each channel is controlled by two independent compare match signals enabling the timer to be used for various applications such as the generation of p...

Page 382: ...0 TCSR_0 TCR_0 TCORA_1 Comparator A_1 TCNT_1 Comparator B_1 TCORB_1 TCSR_1 TCR_1 TMI0 TMCI0 TMI1 TMCI1 TCNT_0 Overflow 1 Overflow 0 Compare match B1 Compare match B0 TMO1 TMI1 TMRI1 Clock selection Co...

Page 383: ...ompare match BX Compare match BY Compare match C Input capture Clock selection Internal bus Control logic Legend TCNT_X TCSR_X TCR_X TICR TCORC TICRR TICRF Timer counter_X Timer control status registe...

Page 384: ...TMCI0 TMRI0 Input External clock input external reset input for the counter TMO1 Output Output controlled by compare match TMR_1 TMI1 TMCI1 TMRI1 Input External clock input external reset input for t...

Page 385: ...8 Channel 0 Timer control status register_0 TCSR_0 R W H 00 H FFCA 8 Timer counter_1 TCNT_1 R W H 00 H FFD1 16 Time constant register A_1 TCORA_1 R W H FF H FFCD 16 Time constant register B_1 TCORB_1...

Page 386: ...TMRX Y bit in TCONRS TCNT_Y TCORA_Y TCORB_Y and TCR_Y can be accessed when the RELOCATE bit in SYSCR3 and the KINWUE bit in SYSCR are cleared to 0 and the TMRX Y bit in TCONRS is set to 1 or when the...

Page 387: ...freely controlled by these compare match A signals and the settings of output select bits OS1 and OS0 in TCSR TCORA is initialized to H FF 13 3 3 Time Constant Register B TCORB TCORB is an 8 bit read...

Page 388: ...bled or disabled when the CMFA flag in TCSR is set to 1 0 CMFA interrupt request CMIA is disabled 1 CMFA interrupt request CMIA is enabled 5 OVIE 0 R W Timer Overflow Interrupt Enable Selects whether...

Page 389: ...dge of internal clock 32 0 1 1 0 Increments at falling edge of internal clock 1024 0 1 1 1 Increments at falling edge of internal clock 256 TMR_0 1 0 0 Increments at overflow signal from TCNT_1 0 0 0...

Page 390: ...xternal clock 1 1 0 Increments at falling edge of external clock Common 1 1 1 Increments at both rising and falling edges of external clock Note If the TMR_0 clock input is set as the TCNT_1 overflow...

Page 391: ...4 0 1 0 0 Increments at 256 0 1 1 0 Increments at 2048 1 0 0 0 Disables clock input 0 0 0 1 Disables clock input 0 0 1 1 Increments at 4096 0 1 0 1 Increments at 8192 0 1 1 1 Increments at 16384 1 0...

Page 392: ...Increments at 4096 0 1 1 1 Increments at 8192 1 0 0 1 Increments at compare match A from TCNT_Y 1 0 1 x Increments at rising edge of external clock 1 1 0 x Increments at falling edge of external cloc...

Page 393: ...ORA_0 match Clearing condition Read CMFA when CMFA 1 then write 0 in CMFA 5 OVF 0 R W Timer Overflow Flag Setting condition When TCNT_0 overflows from H FF to H 00 Clearing condition Read OVF when OVF...

Page 394: ...clearing TCSR_1 Bit Bit Name Initial Value R W Description 7 CMFB 0 R W Compare Match Flag B Setting condition When the values of TCNT_1 and TCORB_1 match Clearing condition Read CMFB when CMFB 1 then...

Page 395: ...0 These bits specify how the TMO1 pin output level is to be changed by compare match A of TCORA_1 and TCNT_1 00 No change 01 0 is output 10 1 is output 11 Output is inverted toggle output Note Only 0...

Page 396: ...signal in that order Clearing condition Read ICF when ICF 1 then write 0 in ICF 3 2 OS3 OS2 0 0 R W R W Output Select 3 and 2 These bits specify how the TMOX pin output level is to be changed by comp...

Page 397: ...A 1 then write 0 in CMFA 5 OVF 0 R W Timer Overflow Flag Setting condition When TCNT_Y overflows from H FF to H 00 Clearing condition Read OVF when OVF 1 then write 0 in OVF 4 ICIE 0 R W Input Capture...

Page 398: ...able writable register The sum of contents of TCORC and TICR is always compared with TCNT When a match is detected a compare match C signal is generated However comparison at the T2 state in the write...

Page 399: ...is set to 1 the contents of TCNT at those points are captured into TICRR and TICRF respectively and the ICST bit is cleared to 0 Clearing condition When a rising edge followed by a falling edge is det...

Page 400: ...R_Y TCR_Y TMR_Y TCSR_Y TMR_Y TCORA_Y TMR_Y TCORB_Y TMR_Y TCNT_Y TMR_Y 13 3 10 Timer XY Control Register TCRXY TCRXY selects the TMR_X and TMR_Y output pins and internal clock Bit Bit Name Initial Valu...

Page 401: ...to 1 so that TCNT is cleared according to the compare match of TCORA 2 Set the OS3 to OS0 bits in TCSR to B 0110 so that 1 is output according to the compare match of TCORA and 0 is output according t...

Page 402: ...ock source The pulse width of the external clock signal must be at least 1 5 system clocks for a single edge and at least 2 5 system clocks for both edges The counter will not increment correctly if t...

Page 403: ...nd TCOR match the compare match signal is not generated until the next TCNT input clock Figure 13 6 shows the timing of CMF flag setting TCNT N N 1 TCOR N Compare match signal CMF Figure 13 6 Timing o...

Page 404: ...ompare match N H 00 Compare match signal TCNT Figure 13 8 Timing of Counter Clear by Compare Match 13 5 5 TCNT External Reset Timing TCNT is cleared at the rising edge of an external reset input depen...

Page 405: ...EJ09B0452 0100 13 5 6 Timing of Overflow Flag OVF Setting The OVF bit in TCSR is set to 1 when the TCNT overflows changes from H FF to H 00 Figure 13 10 shows the timing of OVF flag setting OVF Overfl...

Page 406: ...et for counter clear at compare match the 16 bit counter TCNT_0 and TCNT_1 together is cleared when a 16 bit compare match occurs The 16 bit counter TCNT_0 and TCNT_1 together is also cleared when cou...

Page 407: ...ion If the CCLR1 and CCLR0 bits in TCR_Y have been set for counter clear at compare match only the upper eight bits of TCNT_Y are cleared The upper eight bits of TCNT_Y are also cleared when counter c...

Page 408: ...transferred to both TICRR and TICRF 1 Input Capture Signal Input Timing Figure 13 11 shows the timing of the input capture operation TMRIX Input capture signal TCNT_X n n n m M m N 1 N N n 1 TICRR TIC...

Page 409: ...Signal Input TMRIX input capture input signal of TMR_X is selected according to the setting of the ICST bit in TCONRI The input capture signal selection is shown in table 13 5 Table 13 5 Input Capture...

Page 410: ...ignals are sent to the interrupt controller for each interrupt Table 13 6 Interrupt Sources of 8 Bit Timers TMR_0 TMR_1 TMR_Y and TMR_X Channel Name Interrupt Source Interrupt Flag Interrupt Priority...

Page 411: ...TCNT address Internal write signal Counter clear signal TCNT N H 00 T1 T2 TCNT write cycle by CPU Figure 13 13 Conflict between TCNT Write and Clear 13 9 2 Conflict between TCNT Write and Count Up If...

Page 412: ...input capture takes priority and the compare match signal is disabled Address TCOR address Internal write signal TCNT TCOR N M T1 T2 TCOR write cycle by CPU TCOR write data N N 1 Compare match signal...

Page 413: ...k switching causes a change from high to low level as shown in no 3 in table 13 8 a TCNT clock pulse is generated on the assumption that the switchover is a falling edge and TCNT is incremented Errone...

Page 414: ...ck after switchover TCNT clock TCNT CKS bit rewrite N N 1 N 2 4 4 Clock switching from high to high level Clock before switchover Clock after switchover TCNT clock TCNT CKS bit rewrite N N 1 N 2 Notes...

Page 415: ...0 and TCNT_1 and TCNT_X and TCNT_Y are not generated and thus the counters will stop operating Simultaneous setting of these two modes should therefore be avoided 13 9 7 Module Stop Mode Setting TMR o...

Page 416: ...Section 13 8 Bit Timer TMR Rev 1 00 Apr 28 2008 Page 390 of 994 REJ09B0452 0100...

Page 417: ...function is not needed the WDT can be used as an interval timer In interval timer operation an interval timer interrupt is generated each time the counter overflows A block diagram of the WDT_0 and W...

Page 418: ...control status register_0 TCNT_0 Timer counter_0 TCSR_1 Timer control status register_1 TCNT_1 Timer counter_1 Notes 1 The internal reset signal first resets the WDT in which the overflow has occurre...

Page 419: ...method different from normal registers For details see section 14 6 1 Notes on Register Access For details on the system control register see section 3 2 2 System Control Register SYSCR Table 14 2 Re...

Page 420: ...rflowed changes from H FF to H 00 Setting condition When TCNT overflows changes from H FF to H 00 When internal reset request generation is selected in watchdog timer mode OVF is cleared automatically...

Page 421: ...quested 1 An internal reset is requested 2 1 0 CKS2 CKS1 CKS0 0 0 0 R W R W R W Clock Select 2 to 0 Selects the clock source to be input to TCNT The overflow frequency for 20 MHz is enclosed in parent...

Page 422: ...n to OVF When 0 is written to TME 6 WT IT 0 R W Timer Mode Select Selects whether the WDT is used as a watchdog timer or interval timer 0 Interval timer mode 1 Watchdog timer mode 5 TME 0 R W Timer En...

Page 423: ...6 s 001 64 frequency 819 2 s 010 128 frequency 1 6 ms 011 512 frequency 6 6 ms 100 2048 frequency 26 2 ms 101 8192 frequency 104 9 ms 110 32768 frequency 419 4 ms 111 131072 frequency 1 68 s When PSS...

Page 424: ...equest is generated An internal reset request from the watchdog timer and a reset input from the RES pin are processed in the same vector Reset source can be identified by the XRST bit status in SYSCR...

Page 425: ...can be generated at intervals When the TCNT overflows in interval timer mode an interval timer interrupt WOVI is requested at the same time the OVF flag of TCSR is set to 1 The timing is shown figure...

Page 426: ...Notes on Register Access The watchdog timer s registers TCNT and TCSR differ from other registers in being more difficult to write to The procedures for writing to and reading from these registers are...

Page 427: ...ead in the same way as other registers The read address is H FFA8 for TCSR and H FFA9 for TCNT 14 6 2 Conflict between Timer Counter TCNT Write and Increment If a timer counter clock pulse is generate...

Page 428: ...KS2 to CKS0 bits 14 6 4 Changing Value of PSS Bit If the PSS bit in TCSR_1 is written to while the WDT is operating errors could occur in the operation Stop the watchdog timer by clearing the TME bit...

Page 429: ...d synchronous serial communication mode Full duplex communication capability The transmitter and receiver are mutually independent enabling transmission and reception to be executed simultaneously Dou...

Page 430: ...rect convention and inverse convention are supported Figure 15 1 shows a block diagram of SCI RxD1 TxD1 SCK1 Clock 4 16 64 TEI TXI RXI ERI SCMR SSR SCR SMR Transmission reception control Baud rate gen...

Page 431: ...on Channel Pin Name Input Output Function SCK1 Input Output Channel 1 clock input output RxD1 Input Channel 1 receive data input 1 TxD1 Output Channel 1 transmit data output SCK2 Input Output Channel...

Page 432: ...Abbreviation R W Initial Value Address Data Bus Width Serial mode register_1 SMR_1 R W H 00 H FF88 8 Bit rate register_1 BRR_1 R W H FF H FF89 8 Serial control register_1 SCR_1 R W H 00 H FF8A 8 Tran...

Page 433: ...n to by the CPU The initial value of RDR is H 00 15 3 3 Transmit Data Register TDR TDR is an 8 bit register that stores transmit data When the SCI detects that TSR is empty it transfers the transmit d...

Page 434: ...enabled only in asynchronous mode 0 Selects 8 bits as the data length 1 Selects 7 bits as the data length LSB first is fixed and the MSB of TDR is not transmitted in transmission In clocked synchrono...

Page 435: ...t Rate Register BRR n is the decimal display of the value of n in BRR see section 15 3 9 Bit Rate Register BRR Bit Functions in Smart Card Interface Mode when SMIF in SCMR 1 Bit Bit Name Initial Value...

Page 436: ...ansfer time in smart card interface mode 00 32 clock cycles S 32 01 64 clock cycles S 64 10 372 clock cycles S 372 11 256 clock cycles S 256 For details see section 15 7 4 Receive Data Sampling Timing...

Page 437: ...lue R W Description 7 TIE 0 R W Transmit Interrupt Enable When this bit is set to 1 a TXI interrupt request is enabled 6 RIE 0 R W Receive Interrupt Enable When this bit is set to 1 RXI and ERI interr...

Page 438: ...ource and SCK pin function Asynchronous mode 00 Internal clock SCK pin functions as I O port 01 Internal clock Outputs a clock of the same frequency as the bit rate from the SCK pin 1x External clock...

Page 439: ...Enable When this bit is set to 1 reception is enabled 3 MPIE 0 R W Multiprocessor Interrupt Enable enabled only when the MP bit in SMR is 1 in asynchronous mode Write 0 to this bit in smart card inter...

Page 440: ...er TDR contains transmit data Setting conditions When the TE bit in SCR is 0 When data is transferred from TDR to TSR and TDR is ready for data write Clearing condition When 0 is written to TDRE after...

Page 441: ...ing reception Clearing condition When 0 is written to PER after reading PER 1 2 TEND 1 R Transmit End Setting conditions When the TE bit in SCR is 0 When TDRE 1 at transmission of the last bit of a 1...

Page 442: ...RDRF 0 R W 1 Receive Data Register Full Indicates that receive data is stored in RDR Setting condition When serial reception ends normally and receive data is transferred from RSR to RDR Clearing cond...

Page 443: ...are 0 When ERS 0 and TDRE 1 after a specified time passed after the start of 1 byte data transfer The set timing depends on the register setting as follows When GM 0 and BLK 0 2 5 etu 2 after transmis...

Page 444: ...s valid only when the 8 bit data format is used for transmission reception when the 7 bit data format is used data is always transmitted received with LSB first 2 SINV 0 R W Smart Card Data Invert Spe...

Page 445: ...or Asynchronous mode B 64 2 N 1 2n 1 106 Error 1 100 B 64 2 N 1 2n 1 106 Clocked synchronous mode B 8 2 N 1 2n 1 106 Smart card interface mode B S 2 N 1 2n 1 106 Error B S 2 N 1 1 100 2n 1 106 Legend...

Page 446: ...0 16 19200 0 12 0 16 0 15 0 00 0 15 1 73 0 19 2 34 31250 0 7 0 00 0 9 1 70 0 9 0 00 0 11 0 00 38400 0 7 0 00 0 7 1 73 0 9 2 34 Operating Frequency MHz 12 288 14 14 7456 16 Bit Rate bit s n N Error n...

Page 447: ...6 2400 0 223 0 00 0 233 0 16 0 255 0 00 1 64 0 16 4800 0 111 0 00 0 116 0 16 0 127 0 00 0 129 0 16 9600 0 55 0 00 0 58 0 69 0 63 0 00 0 64 0 16 19200 0 27 0 00 0 28 1 02 0 31 0 00 0 32 1 36 31250 0 16...

Page 448: ...288 3 0720 192000 19 6608 4 9152 307200 14 3 5000 218750 20 5 0000 312500 Table 15 7 BRR Settings for Various Bit Rates Clocked Synchronous Mode Operating Frequency MHz 8 10 16 20 Bit Rate bit s n N...

Page 449: ...3333333 3 14 2 3333 2333333 3 Table 15 9 BRR Settings for Various Bit Rates Smart Card Interface Mode n 0 s 372 Operating Frequency MHz 10 00 13 00 14 2848 16 00 Bit Rate bit s n N Error n N Error n N...

Page 450: ...the space state low level recognizes a start bit and starts serial communication Inside the SCI the transmitter and receiver are independent units enabling full duplex communication Both the transmit...

Page 451: ...e 15 11 Serial Transfer Formats Asynchronous Mode PE 0 0 1 1 0 0 1 1 S 8 bit data STOP S 7 bit data STOP S 8 bit data STOPSTOP S 8 bit data P STOP S 7 bit data STOP P S 8 bit data MPB STOP S 8 bit dat...

Page 452: ...h bit as shown in figure 15 3 Thus the reception margin in asynchronous mode is determined by formula 1 below M 0 5 1 F L 0 5 F 100 Formula 1 2N 1 N D 0 5 M Reception margin N Ratio of bit rate to clo...

Page 453: ...CKE0 bits in SCR When an external clock is input at the SCK pin the clock frequency should be 16 times the bit rate used When the SCI is operated on an internal clock the clock can be output from the...

Page 454: ...plied even during initialization Wait Initialization completion Start initialization Set data transfer format in SMR and SCMR 1 Set CKE1 and CKE0 bits in SCR TE and RE bits are 0 No Yes Set value in B...

Page 455: ...rder start bit transmit data parity bit or multiprocessor bit may be omitted depending on the format and stop bit 4 The SCI checks the TDRE flag at the timing for sending the stop bit 5 If the TDRE fl...

Page 456: ...smission is enabled 2 SCI status check and transmit data write Read SSR and check that the TDRE flag is set to 1 then write transmit data to TDR and clear the TDRE flag to 0 3 Serial transmission cont...

Page 457: ...ed to RDR If the RIE bit in SCR is set to 1 at this time an ERI interrupt request is generated 4 If a framing error when the stop bit is 0 is detected the FER bit in SSR is set to 1 and receive data i...

Page 458: ...ER and RDRF bits to 0 before resuming reception Figure 15 9 shows a sample flowchart for serial data reception Table 15 12 SSR Status Flags and Receive Data Handling SSR Status Flag RDRF ORER FER PER...

Page 459: ...processing ensure that the ORER PER and FER flags are all cleared to 0 Reception cannot be resumed if any of these flags are set to 1 In the case of a framing error a break can be detected by reading...

Page 460: ...REJ09B0452 0100 End 3 6 Error processing Parity error processing Yes No Clear ORER PER and FER flags in SSR to 0 No Yes No Yes Framing error processing No Yes Overrun error processing ORER 1 FER 1 Br...

Page 461: ...nsmitting station first sends the ID code of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added It then sends transmit data as data wit...

Page 462: ...eceiving station D ID 01 ID 02 ID 03 ID 04 Serial communication line Serial data ID transmission cycle receiving station specification Data transmission cycle Data transmission to receiving station sp...

Page 463: ...E flag to 0 1 SCI initialization The TxD pin is automatically designated as the transmit data output pin After the TE bit is set to 1 a frame of 1s is output and transmission is enabled 2 SCI status c...

Page 464: ...ata 1 MPB Stop bit Data ID2 Start bit Stop bit Start bit Data Data 2 Stop bit RXI interrupt request multiprocessor interrupt generated Idle state mark state RDRF RDR data read and RDRF flag cleared to...

Page 465: ...to 1 then read the receive data in RDR and compare it with this station s ID If the data is not this station s ID set the MPIE bit to 1 again and clear the RDRF flag to 0 If the data is this station...

Page 466: ...440 of 994 REJ09B0452 0100 End Error processing Yes No Clear ORER PER and FER flags in SSR to 0 No Yes No Yes Framing error processing Overrun error processing ORER 1 FER 1 Break Clear RE bit in SCR t...

Page 467: ...full duplex communication by use of a common clock Both the transmitter and the receiver also have a double buffered structure so that the next transmit data can be written during transmission or the...

Page 468: ...itialization Set data transfer format in SMR and SCMR No Yes Set value in BRR Clear TE and RE bits in SCR to 0 1 3 Set TE and RE bits in SCR to 1 andset RIE TIE TEIE and MPIE bits 4 1 bit interval ela...

Page 469: ...can be enabled 3 8 bit data is sent from the TxD pin synchronized with the output clock when output clock mode has been specified and synchronized with the input clock when use of an external clock h...

Page 470: ...d clear TDRE flag in SSR to 0 No Yes No Yes Read TEND flag in SSR 3 Clear TE bit in SCR to 0 TDRE 1 All data transmitted TEND 1 1 SCI initialization The TxD pin is automatically designated as the tran...

Page 471: ...mains to be set to 1 3 If reception finishes successfully the RDRF bit in SSR is set to 1 and receive data is transferred to RDR If the RIE bit in SCR is set to 1 at this time an RXI interrupt request...

Page 472: ...read the ORER flag in SSR and after performing the appropriate error processing clear the ORER flag to 0 Transfer cannot be resumed if the ORER flag is set to 1 4 SCI status check and receive data re...

Page 473: ...ations To switch from transmit mode to simultaneous transmit and receive mode after checking that the SCI has finished transmission and the TDRE and TEND flags in SSR are set to 1 clear the TE bit in...

Page 474: ...ng the appropriate error processing clear the ORER flag to 0 Transmission reception cannot be resumed if the ORER flag is set to 1 4 SCI status check and receive data read Read SSR and check that the...

Page 475: ...the figure since this LSI communicates with the IC card using a single transmission line interconnect the TxD and RxD pins and pull up the data transmission line to VCC using a resistor Setting the RE...

Page 476: ...etu after 10 5 etu has passed from the start bit If an error signal is sampled during transmission the same data is automatically re transmitted after two or more etu Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp In...

Page 477: ...rse convention type write 1 to both the SDIR and SINV bits in SCMR The parity bit is logic level 0 to produce even parity which is prescribed by the smart card standard and corresponds to state Z Sinc...

Page 478: ...n Receive data is sampled at the 16th 32nd 186th and 128th rising edges of the basic clock pulses so that it can be latched at the center of each bit as shown in figure 15 25 The reception margin here...

Page 479: ...diagnosis To switch from reception to transmission first verify that reception has completed and initialize the SCI At the end of initialization RE and TE should be set to 0 and 1 respectively Recepti...

Page 480: ...ally transmit the specified number of bytes including re transmission in the case of error However the ERS flag is not automatically cleared the ERS flag must be cleared by previously setting the RIE...

Page 481: ...B0452 0100 Initialization No Yes Clear TE bit in SCR to 0 Start transmission Start No No No Yes Yes Yes Yes No End Write data to TDR and clear TDRE flag in SSR to 0 Error processing Error processing T...

Page 482: ...ined to have been received successfully and the RDRF bit in SSR is set to 1 Here an RXI interrupt request is generated if the RIE bit in SCR is set Figure 15 30 shows a sample flowchart for reception...

Page 483: ...Page 457 of 994 REJ09B0452 0100 Initialization Read data from RDR and clear RDRF flag in SSR to 0 Clear RE bit in SCR to 0 Start reception Start Error processing No No No Yes Yes ORER 0 and PER 0 RDR...

Page 484: ...idth SCK CKE0 Specified pulse width Figure 15 31 Clock Output Fixing Timing At power on and transitions to from software standby mode use the following procedure to secure the appropriate clock duty r...

Page 485: ...to the value for the output fixed state in software standby mode 3 Write 0 to the CKE0 bit in SCR to stop the clock 4 Wait for one cycle of the serial clock In the mean time the clock output is fixed...

Page 486: ...an RXI interrupt request is generated When the ORER PER or FER flag in SSR is set to 1 an ERI interrupt request is generated A TEI interrupt is requested when the TEND flag is set to 1 while the TEIE...

Page 487: ...ND and TDRE flags in SSR are simultaneously set to 1 thus generating a TXI interrupt request If an error occurs the SCI automatically re transmits the same data During re transmission the TEND flag re...

Page 488: ...transmission To maintain the communication line at mark state until TE is set to 1 set both DDR and DR to 1 Since the TE bit is cleared to 0 at this point the TxD pin becomes an I O port and 1 is outp...

Page 489: ...te to TDR clear TDRE in this order and then start transmission To transmit data in a different transmission mode initialize the SCI first Figure 15 33 shows a sample flowchart for mode transition duri...

Page 490: ...I TxD output Port Port SCI TxD output Figure 15 34 Pin States during Transmission in Asynchronous Mode Internal Clock TE bit SCK output pin TxD output pin Port input output Port input output Port inpu...

Page 491: ...cancellation set RE to 1 and then start reception To receive data in a different reception mode initialize the SCI first Figure 15 36 shows a sample flowchart for mode transition during reception Star...

Page 492: ...6 Bit 7 Low pulse of half a cycle Figure 15 37 Switching from SCK Pins to Port Pins To prevent the low pulse output that is generated when switching the SCK pins to the port pins specify the SCK pins...

Page 493: ...is set to the TE and RE bits in SCR to start transmission reception and simultaneous transmission and reception do not write to SMR SCR BRR and SDCR Also do not overwrite the same value as the registe...

Page 494: ...Section 15 Serial Communication Interface SCI Rev 1 00 Apr 28 2008 Page 468 of 994 REJ09B0452 0100...

Page 495: ...C format Sampling clock selectable Selectable from internal clocks 2 and 4 and subclock SUB Noise canceling function Input noise can be filtered out by using a maximum of four stages of filters Polari...

Page 496: ...register HHMAX Header maximum high level period register HLMIN Header minimum low level period register HLMAX Header maximum low level period register DT1MIN Data level 1 minimum period register DT1MA...

Page 497: ...H FA41 Receive status register CSTR R W H 00 H FA42 Interrupt enable register CEIR R W H 00 H FA43 Bit rate register BRR R W H FF H FA44 Receive data register 0 to 17 CIRRDR0 to CIRRDR17 R H 00 H FA4...

Page 498: ...CIR input signals and select the reference clock for CIR reception Bit Bit Name Initial Value R W Description 7 CIRE 0 R W CIR Receive Enable 0 The CIR reception is disabled 1 The CIR reception is ena...

Page 499: ...ged 1 0 CLK1 CLK0 0 0 R W R W Reference Clock 00 Internal clock 01 Internal clock 2 10 Internal clock 4 11 subclock sub 16 3 2 Receive Control Register 2 CCR2 CCR2 consists of the bits that select the...

Page 500: ...RF 0 R Receive Data Register Full Indicates whether CIRRDR contains a receive data or not This bit cannot be modified Setting condition When a receive data is stored into CIRRDR Clearing condition Whe...

Page 501: ...rated when an abort transfer format is detected Setting condition When data other than logic 0 or 1 is detected Clearing condition When writing 0 after reading ABF 1 1 FRF 0 R W Framing Error Flag Set...

Page 502: ...s enabled 4 OVEIE 0 R W Overrun Error Interrupt Enable 0 OVEI interrupt request is disabled 1 OVEI interrupt request is enabled 3 RENDIE 0 R W Receive End Interrupt Enable 0 RENDI interrupt request is...

Page 503: ...clock The following formula is used for calculating the bit rate and the following table shows BRR setting examples to obtain a target bit rate B T N 1 B Bit rate bits s T Frequency of the reference...

Page 504: ...circuit and specify the minimum and maximum high level period for a header or repeat header and low level period for a stop HHMIN Bit Bit Name Initial Value R W Description 15 to 11 RFMBN4 to RFMBN0...

Page 505: ...circuit consists of four stages 13 FLTE 0 R W Noise Canceler Circuit Enable 0 Disables the noise canceler circuit 1 Enables the noise canceler circuit 12 11 FLTCK1 FLTCK0 0 0 R W R W Division Ratio S...

Page 506: ...der HLMAX Bit Bit Name Initial Value R W Description 7 to 0 HLMAX7 to HLMAX0 H 00 R W Specifies the maximum low level period for a header 16 3 9 Data Level 1 Minimum Maximum Period Register DT1MIN DT1...

Page 507: ...h level period for a stop repeat DT0MAX Bit Bit Name Initial Value R W Description 7 to 0 DT0MAX7 to DT0MAX0 H 00 R W Specifies the maximum low high level period for logic 0 high level period for logi...

Page 508: ...Stop CIRI Figure 16 2 NEC Format 1 Header Address and Command When a 9 ms high level and the following 4 5 ms low level are detected they are recognized as a header For addresses and commands when bot...

Page 509: ...0 1 low level period for logic 0 and high level period for a stop D Low level period for logic 1 Legend Figure 16 4 Stop 3 Repeat When a key of the remote controller remains pressed the command is se...

Page 510: ...ating formula for specified time setting examples of each maximum minimum value register during the specified time and use for each register are described as follows The symbols in table 16 4 correspo...

Page 511: ...3 20 ms 3 15 ms Maximum low level period for a header HLMAX B H 6F 5 82 ms 5 85 ms Minimum value of low high level period for logic 0 high level period for logic 1 and high level period for a burst D...

Page 512: ...18 FIFO contents Byte 0 H 00 H 00 H 00 H 00 Number of bytes 1 2 3 4 18 FIFO contents Byte 0 Operation for first reception of data Operation for data reception three times Byte 1 Byte 2 H 00 H 00 Figu...

Page 513: ...settings for the mode transition Select the subclock sub as the operating clock for the CIR module Enable the CIR header detected interrupt For a transition from watch mode to high speed mode the CIR...

Page 514: ...ct the number of stages of the noise canceler circuit and select the division ratio for generating the noise canceler circuit clock respectively Figure 16 6 shows a block diagram of the noise canceler...

Page 515: ...tages of Noise Canceler Circuit Width of Noise Cancellation 10 MHz H 80 Not divided 12 9 s 0 12 9 s 1 25 8 s 2 38 7 s 3 51 6 s 4 64 5 s Divided by 2 25 8 s 0 25 8 s 2 77 4 s 4 129 s Divided by 4 51 6...

Page 516: ...zed Initialized Abort Retained Retained Retained Retained CIRBUSY is initialized Initialized Retained 16 7 Interrupt Sources The CIR has six interrupt source flags for this LSI Setting the correspondi...

Page 517: ...CPHS bit in CCR1 should be set before starting reception When the CIRI pin is high in the idle state set the CPHS bit to 1 When it is low in the idle state clear the bit to 0 The BRR register is initi...

Page 518: ...mat 2 Bytes are Used When the reception signal format select bits bits TFM1 and TFM0 in CCR2 are set to the NEC format 2 bytes are used the OVRF bit in CSTR is set to indicate the overrun on the recep...

Page 519: ...de efficient high speed continuous communication In addition the SCIF can be connected to the LPC interface for direct control from the LPC host 17 1 Features Full duplex communication The transmitter...

Page 520: ...lock SCIFCR FIER FIIR FFCR FLCR FMCR FLSR FMSR FSCR Register transmission reception control SCIF interrupt request System clock LCLK Receive FIFO 16 bytes Reception 1 byte Legend FRSR Receive shift re...

Page 521: ...s Table 17 1 Pin Configuration Pin Name Port Input Output Function FTxD P50 Output Transmit data output FRxD P51 Input Receive data input RI PB2 Input Ring indicator input DCD PB3 Input Data carrier d...

Page 522: ...ICR5 R W H 00 H FFFE33 8 Module stop control register B MSTPCRB R W H 00 H FFFE7F 8 Receive buffer register FRBR R H 00 Transmitter holding register FTHR W Divisor latch L FDLL R W H 00 H FFFC20 8 Int...

Page 523: ...the order received from the LSB bit 0 When one frame of serial data has been received the data is transferred to FRBR FRSR cannot be read from the CPU LPC interface 17 3 2 Receive Buffer Register FRB...

Page 524: ...t to 1 Data can be written to FTHR when the THRE bit is set with the FIFO disabled If data is written to FTHR when the THRE bit is not set the data is overwritten While the THRE bit is set with the FI...

Page 525: ...nitial Value R W Description 7 to 4 All 0 R Reserved This bit is always read as 0 and cannot be modified 3 EDSSI 0 R W Modem Status Interrupt Enable 0 Modem status interrupt disabled 1 Modem status in...

Page 526: ...e FIFO setting 00 Transmit receive FIFOs disabled 11 Transmit receive FIFOs enabled 5 4 All 0 R Reserved These bits are always read as 0 and cannot be modified 3 2 1 INTID2 INTID1 INTID0 0 0 0 R R R I...

Page 527: ...Receive line status Overrun error parity error framing error break interrupt FLSR read 0 1 0 0 2 Receive data ready Receive data remaining FIFO trigger level FRBR read or receive FIFO is below trigger...

Page 528: ...00 1 byte 01 4 bytes 10 8 bytes 11 14 bytes 5 4 Reserved These bits cannot be modified 3 DMAMODE 0 DMA Mode This bit is not supported and cannot be modified 2 XMITFRST 0 W Transmit FIFO Reset The tran...

Page 529: ...FDLH access enabled 6 BREAK 0 R W Break Control Generates a break by driving the serial output signal FTxD low The break state is released by clearing this bit 0 Break released 1 Break generated 5 STI...

Page 530: ...7 3 10 Modem Control Register FMCR FMCR controls output signals Bit Bit Name Initial Value R W Description 7 to 5 All 0 R Reserved These bits are always read as 1 and cannot be modified 4 LOOP BACK 0...

Page 531: ...t 0 Interrupt disabled 1 Interrupt enabled Loopback test Internally connected to the DCD input pin 2 OUT1 0 R W OUT1 Normal operation No effect on operation Loopback test Internally connected to the R...

Page 532: ...at could cause an error after an FIFO clear 1 A receive FIFO error Setting condition When at least one data error parity error framing error or break interrupt has occurred in the FIFO 6 TEMT 1 R Tran...

Page 533: ...nsmit data remains in FTHR Clearing condition Transmit data is written to FTHR 1 No transmit data in FTHR Setting condition When data transfer from FTHR to FTSR is completed 4 BI 0 R Break Interrupt I...

Page 534: ...umes that the framing error is due to the next start bit samples the start bit and treats it as a start bit 0 No framing error Clearing condition FLSR read 1 A framing error Setting condition Invalid...

Page 535: ...ror occurs and the previous data is lost When the FIFO is enabled When the FIFO is full and reception of the next data has been completed an overrun error occurs The FIFO data is retained but the last...

Page 536: ...the inverted state of the DSR input pin 4 CTS Undefined R Clear to Send Indicates the inverted state of the CTS input pin 3 DDCD 0 R Delta Data Carrier Indicator Indicates a change in the DCD input s...

Page 537: ...after FMSR read Setting condition A change in the DSR input signal 0 DCTS 0 R Delta Clear to Send Indicator Indicates a change in the CTS input signal after the DCTS bit is read 0 No change in the CTS...

Page 538: ...d Do not change the initial value 4 OUT2LOOP 0 R W Enables or disables interrupts during a loopback test 0 Interrupt enabled 1 Interrupt disabled 3 2 CKSEL1 CKSEL0 0 0 R W R W These bits select the cl...

Page 539: ...tput Setting Bit 3 in HICR5 0 0 0 0 1 1 1 1 Bit 7 in SCIFCR 0 0 1 1 0 0 1 1 Bit 6 in SCIFCR 0 1 0 1 0 1 0 1 PB7 and PB5 pins PORT PORT SCIF PORT SCIF PORT SCIF PORT P50 pin PORT PORT SCIF SCIF SCIF SC...

Page 540: ...k 20 MHz divided by 11 System Clock 10 MHz divided by 11 Baud rate FDLH FDLL Hex Error FDLH FDLL Hex Error FDLH FDLL Hex Error 50 0900 0 54 0900 1 36 0480 1 36 75 0600 0 54 0600 1 36 0300 1 36 110 041...

Page 541: ...n line and when it detects the space state low level recognizes a start bit and starts serial communication Inside the SCIF the transmitter and receiver are independent units enabling full duplex comm...

Page 542: ...No Select an input clock with the CKSEL1 and CKSEL0 bits in SCIFCR Set the SCIF input output pins with the SCIFOE1 and SCIFOE0 bits in SCIFCR Set the DLAB bit in FLCR to 1 to enable access to FDLL an...

Page 543: ...HRE flag in FLSR is 1 and write transmit data to FTHR When FIFOs are used write 1 byte to 16 byte transmit data When the OUT2 bit in FMCR and the ETBEI bit in FIER are set to 1 an FTHR empty interrupt...

Page 544: ...0 1 Confirm that the DR flag in FLSR is 1 to ensure that receive data is in the buffer When the OUT2 bit in FMCR and the ERBFI bit in FIER are set to 1 a receive data ready interrupt occurs 2 Read the...

Page 545: ...L0 bits in SCIFCR Set the SCIF input output pins with the SCIFOE1 and SCIFOE0 bits in SCIFCR 2 Set the DLAB bit in FLCR to 1 to enable access to FDLL and FDLH 3 The initial value of FDLL and FDLH is 0...

Page 546: ...xample of the data transmission reception standby flowchart No No Yes Transmit data exists Transmission flow Reception flow Yes Initialization 1 2 1 When a receive data ready interrupt occurs go to th...

Page 547: ...ransmission or transmission standby Yes Transmission reception standby 1 2 3 4 1 Confirm that the CTS flag in FMSR is 1 2 Confirm that the THRE flag in FLSR is 1 to ensure that the transmit FIFO is em...

Page 548: ...ransmit FIFO Set XMITFRST bit in FFCR to 1 Other processing Prepare for retransmission Transmission flow DCTS 1 No Yes 1 2 3 4 1 Read the DCTS flag in FMSR in the modem status change interrupt process...

Page 549: ...tandby flow BI 1 FE 1 PE 1 or OE 1 DR 0 No Yes 1 2 3 4 1 When data is received a receive data ready interrupt occurs Go to the data reception flow by using this interrupt trigger 2 Confirm that the BI...

Page 550: ...Read FLSR Set RTS bit in FMCR to 1 Transmission reception standby flow DR 0 No Yes 1 2 3 4 1 When data is received at a trigger level higher than the receive FIFO trigger level specified in the initia...

Page 551: ...interface Table 17 7 shows the correspondence between LPC interface I O address and access to the SCIF registers For details of the LPC interface settings see section 20 LPC interface LPC Table 17 7 C...

Page 552: ...3 to 0 Initialized Retained Retained Retained Retained Retained SCIFCR SCIFOE1 SCIFOE0 OUT2LOOP CKSEL1 CKSEL0 SCIFRST REGRST Initialized Retained Retained Retained Retained Retained FRBR Bits 7 to 0 I...

Page 553: ...Retained Initialized Initialized Retained Retained FLSR RXFEFOERR TEMT THRE BI FE PE OE DR Initialized Retained Initialized Initialized Retained Retained FMSR DDCD TERI DDSR DCTS Initialized Retained...

Page 554: ...tance of receive data FIFO trigger level Character timeout when FIFO is enabled No data is input to or output from the receive FIFO for the 4 character time period while one or more characters remain...

Page 555: ...e I2 C bus format Selection of the acknowledge output level in reception I2 C bus format Automatic loading of an acknowledge bit in transmission I2 C bus format Wait function in master mode I2 C bus f...

Page 556: ...ction is selected Note When using this IIC module make sure to set bits HNDS FNC1 and FNC0 in ICXR to 1 in the initial settings If other settings are made restrictions on operation that are not covere...

Page 557: ...or SAR SARX SDA Noise canceler Interrupt generator Interrupt request Internal data bus ICDRR ICDRT Legend ICCR ICMR ICSR ICDR ICXR SAR SARX PS Note An input output pin can be selected among three pins...

Page 558: ...32 of 994 REJ09B0452 0100 SCL in SCL out SDA in SDA out Slave 1 SCL SDA SCL in SCL out SDA in SDA out Slave 2 SCL SDA SCL in SCL out SDA in SDA out Master This LSI SCL SDA VCC VCC SCL SDA VDD Figure 1...

Page 559: ...0 Input Output Serial clock input output pin of IIC_0 0 SDA0 Input Output Serial data input output pin of IIC_0 SCL1 Input Output Serial clock input output pin of IIC_1 1 SDA1 Input Output Serial data...

Page 560: ...ended control register_0 ICXR_0 R W H 00 H FED4 8 I 2 C bus control register_0 ICCR_0 R W H 01 H FFD8 8 I 2 C bus status register_0 ICSR_0 R W H 00 H FFD9 8 I 2 C bus data register_0 ICDR_0 R W H FFDE...

Page 561: ...rol register_2 ICCR_2 R W H 01 H FE88 8 I 2 C bus status register_2 ICSR_2 R W H 00 H FE89 8 I 2 C bus data register_2 ICDR_2 R W H FE8E 8 Second slave address register_2 SARX_2 R W H 01 H FE8E 8 I 2...

Page 562: ...T to ICDRS and the ICDRE flag is set to 1 As long as ICDRS contains data to be transmitted or data being transmitted data written to ICDRT are retained there In receive mode TRS 0 data is not transfer...

Page 563: ...st frame received after a start condition the LSI operates as the slave device specified by the master device SAR can be accessed only when the ICE bit in ICCR is cleared to 0 Bit Bit Name Initial Val...

Page 564: ...RX match the upper 7 bits of the first frame received after a start condition the LSI operates as the slave device specified by the master device SARX can be accessed only when the ICE bit in ICCR is...

Page 565: ...at SAR slave address recognized SARX slave address ignored General call address recognized 0 I 2 C bus format SAR slave address ignored SARX slave address recognized General call address ignored 1 1 C...

Page 566: ...de with the I 2 C bus format 0 Data and the acknowledge bit are transferred consecutively with no wait inserted 1 After the fall of the clock for the final data bit 8 th clock the IRIC flag is set to...

Page 567: ...interval between transfer frames If bits BC2 to BC0 are set to a value other than 000 the setting should be made while the SCL line is low The bit counter is initialized to B 000 when a start conditio...

Page 568: ...0 kHz 160 kHz 200 kHz 0 1 1 0 112 71 4 kHz 89 3 kHz 143 kHz 179 kHz 0 1 1 1 128 62 5 kHz 78 1 kHz 125 kHz 156 kHz 1 0 0 0 56 143 kHz 179 kHz 286 kHz 357 kHz 1 0 0 1 80 100 kHz 125 kHz 200 kHz 250 kHz...

Page 569: ...Interrupt Enable 0 Disables interrupts from the I 2 C bus interface to the CPU 1 Enables interrupts from the I 2 C bus interface to the CPU 5 4 MST TRS 0 0 R W R W Master Slave Select Transmit Receiv...

Page 570: ...us contention in I2 C bus format master mode TRS setting conditions 1 When 1 is written by software except for TRS clearing condition 3 2 When 1 is written in TRS after reading TRS 0 for TRS clearing...

Page 571: ...h to low under the condition of SCL high assuming that the start condition has been issued BBSY clearing condition When the SDA level changes from low to high under the condition of SCL high assuming...

Page 572: ...nsmit mode and the ICDRE flag is set to 1 3 When data is transferred from ICDRS to ICDRR in receive mode and the ICDRF flag is set to 1 4 If 1 is received as the acknowledge bit when the ACKE bit is 1...

Page 573: ...gs of AAS AASX and ADZ cleared to 0 transmission and reception do not proceed Thus the ICDRE and ICDRF flags will not be set Nor will the IRIC flag However even in this case if STOPIM is 0 the IRIC fl...

Page 574: ...5 Flags and Transfer States Master Mode MST TRS BBSY ESTP STOP IRTR AASX AL AAS ADZ ACKB ICDRF ICDRE State 1 1 0 0 0 0 0 0 0 0 0 0 Idle state flag clearing required 1 1 1 0 0 1 0 0 0 0 0 1 Start cond...

Page 575: ...9 of 994 REJ09B0452 0100 MST TRS BBSY ESTP STOP IRTR AASX AL AAS ADZ ACKB ICDRF ICDRE State 0 0 1 0 0 0 1 0 0 Arbitration lost 1 0 0 0 0 0 0 0 0 Stop condition detected Legend 0 0 state retained 1 1 s...

Page 576: ...0 1 1 0 0 0 0 0 0 0 ICDR write with the above state 0 1 1 0 0 1 0 1 Transmission end with ICDRE 1 0 1 1 0 0 0 0 0 0 0 ICDR write with the above state 0 1 1 0 0 1 0 2 0 0 0 0 1 Automatic data transfer...

Page 577: ...condition When a stop condition is detected after frame transfer completion Clearing conditions When 0 is written in STOP after reading STOP 1 When the IRIC flag is cleared to 0 5 IRTR 0 R W I 2 C Bu...

Page 578: ...t condition is detected In master mode 3 AL 0 R W Arbitration Lost Flag Indicates that arbitration was lost in master mode Setting conditions When ALSL 0 If the internal SDA and SDA pin disagree at th...

Page 579: ...is written to transmit mode or read from receive mode When 0 is written in AAS after reading AAS 1 In master mode 1 ADZ 0 R W General Call Address Recognition Flag In I 2 C bus format slave receive mo...

Page 580: ...s bit is read the value loaded from the bus line returned by the receiving device is read in transmission when TRS 1 In reception when TRS 0 the value set by internal software is read When this bit is...

Page 581: ...alid setting Controls initialization of the internal state of IIC_2 ICRES_2 00 Setting prohibited 0100 Setting prohibited 0101 IIC_2 internal latch cleared 0110 Setting prohibited 0111 IIC_2 internal...

Page 582: ...e stop condition is detected 6 HNDS 0 R W Enables or disables handshake control in receive mode for the selection of reception with handshaking 0 Disables handshake control 1 Enables handshake control...

Page 583: ...ICDRS to ICDRR 1 When data is received successfully while ICDRF 0 at the rise of the 9th clock pulse 2 When ICDR is read successfully in receive mode after data was received while ICDRF 1 Clearing co...

Page 584: ...a transmission completed while ICDRE 0 at the rise of the 9th clock pulse 2 When data is written to ICDR in transmit mode after data transmission was completed while ICDRE 1 Clearing conditions When d...

Page 585: ...0 When the SDA pin state disagrees with the data that IIC bus interface outputs at the rise of SCL or when the SCL pin is driven low by another device 1 When the SDA pin state disagrees with the data...

Page 586: ...figure 18 4 Figure 18 5 shows the I2 C bus timing The symbols used in figures 18 3 to 18 5 are explained in table 18 7 S A SLA 7 n R W DATA A 1 1 m 1 1 1 A A 1 P 1 Transfer bit count n 1 to 8 Transfe...

Page 587: ...irection of data transfer from the slave device to the master device when R W is 1 or from the master device to the slave device when R W is 0 A Acknowledge The receiving device drives SDA low to ackn...

Page 588: ...mmunication operation STOPIM HNDS ALIE ALSL FNC1 and FNC0 Be sure to set as follows HNDS 1 FNC1 1 and FNC0 1 Set acknowledge bit ACKB Set ICMR Set ICCR Set IICE 1 in STCR Set SAR and SARX Set ICE 1 in...

Page 589: ...lag continuously 2 Test the status of the SCL and SDA lines 7 Wait for 1 byte to be transmitted 10 Wait for 1 byte to be transmitted 11 Determine end of tranfer 12 Stop condition issuance 8 Test the a...

Page 590: ...ed slave device i e the slave device with the matching slave address drives SDA low at the 9th transmit clock pulse and returns an acknowledge signal 7 When one frame of data has been transmitted the...

Page 591: ...DA slave output 2 1 R W 4 3 6 5 8 7 1 2 9 A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 ICDRE IRTR ICDRT Note Data write in ICDR prohibited SCL master output Start condition generation...

Page 592: ...6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 0 ICDRE IRTR ICDR SCL master output Stop condition issuance Data 2 9 ICDR write 9 IRIC clear 12 IRIC clear 11 ACKB read 12 Set BBSY 0 and SCP 0 Stop condition...

Page 593: ...g in ICCR Clear IRIC flag in ICCR Clear IRIC flag in ICCR Clear IRIC flag in ICCR Set BBSY 0 and SCP 0 in ICCR IRIC 1 No Yes Yes Read ICDR No 4 Clear IRIC flag 1 Select receive mode 2 Start receiving...

Page 594: ...RIC and IRTR flags to 1 If the IEIC bit has been set to 1 an interrupt request is sent to the CPU The master device drives SCL low from the fall of the 9th receive clock pulse to the ICDR data reading...

Page 595: ...DR read Data 1 Undefined value Figure 18 11 Example of Operation Timing in Master Receive Mode MLS WAIT 0 SDA master output SDA slave output 2 1 4 3 6 5 8 7 9 9 7 8 A A Bit 7 Bit 1 Bit 6 Bit 5 Bit 4 B...

Page 596: ...tputs the transmit clock and transmit data and the slave device returns an acknowledge signal The slave device operates as the device specified by the master device when the slave address in the first...

Page 597: ...es No AAS 1 and ADZ 1 Read IRIC flag in ICCR IRIC 1 ESTP 1 or STOP 1 No Yes No 1 Initialization Select slave receive mode 2 Read the receive data remaining unread 3 to 7 Wait for one byte to be receiv...

Page 598: ...the slave address does not match receive operation is halted until the next start condition is detected 5 At the 9th clock pulse of the receive frame the slave device returns the data in the ACKB bit...

Page 599: ...is fixed low until ICDR is read 2 ICDR read Interrupt request occurrence Figure 18 14 Example of Slave Receive Mode Operation Timing 1 MLS 0 SDA master output SDA slave output 2 1 4 3 6 5 8 7 9 8 9 Bi...

Page 600: ...to 0 in ICCR ACKB 0 clear Clear IRIC in ICCR Read IRIC in ICCR Read ACKB in ICSR Set TRS 0 in ICCR Read ICDR Read IRIC in ICCR IRIC 1 Yes Yes No No IRIC 1 Yes No 1 2 If the slave address matches to t...

Page 601: ...e set to 1 again The slave device sequentially sends the data written into ICDRS in accordance with the clock output by the master device The IRIC flag is cleared to 0 to detect the end of transmissio...

Page 602: ...A is changed from low to high when SCL is high the BBSY flag in ICCR is cleared to 0 and the STOP flag in ICSR is set to 1 When the STOPIM bit in ICXR is 0 the IRIC flag is set to 1 If the IRIC flag h...

Page 603: ...een transferred in synchronization with the internal clock Figures 18 18 to 18 20 show the IRIC set timing and SCL control SCL SDA IRIC User processing Clear IRIC 2 3 1 A 8 7 3 2 1 9 8 7 When WAIT 0 a...

Page 604: ...or ICDRF 0 at reception b Data transfer ends with ICDRE 1 at transmission or ICDRF 1 at reception Figure 18 19 IRIC Setting Timing and SCL Control 2 SCL SDA IRIC User processing Clear IRIC 1 8 7 4 1...

Page 605: ...atch SCL or SDA input signal Match detector Internal SCL or SDA signal Sampling clock Figure 18 21 Block Diagram of Noise Canceler 18 4 9 Initialization of Internal State The IIC has a function for fo...

Page 606: ...written to simultaneously in accordance with the setting If a flag clearing setting is made during transmission reception the IIC module will stop transmitting receiving at that point and the SCL and...

Page 607: ...led or disabled using the enable bits in ICCR and are sent to the interrupt controller independently The IIC interrupts are used as on chip DTC activation sources Table 18 8 IIC Interrupt Sources Chan...

Page 608: ...A outputs in synchronization with the internal clock Timings on the bus are determined by the rise and fall times of signals affected by the bus load capacitance series resistance and parallel resista...

Page 609: ...e specifications for the SCL and SDA rise and fall times are under 1000 ns and 300 ns The I2 C bus interface SCL and SDA output timing is prescribed by tcyc as shown in table 18 11 However because of...

Page 610: ...1000 250 3325 3400 3513 3550 tSDASO master 1 tSCLLO 3 3 tcyc tSr High speed mode 300 100 625 700 813 850 Standard mode 1000 250 2200 2500 2950 3100 tSDASO slave 1 tSCLL 3 12 tcyc 2 tSr High speed mode...

Page 611: ...dress does not match Similarly if the start condition or address is transmitted from the master device in slave transmit mode TRS 1 the IRIC flag may be set after the ICDRE flag is set and 1 received...

Page 612: ...Section 18 I 2 C Bus Interface IIC Rev 1 00 Apr 28 2008 Page 586 of 994 REJ09B0452 0100...

Page 613: ...nsfer using the PS2 employs a data line KD and a clock line KCLK providing economical use of connectors board surface area etc Figure 19 1 shows a block diagram of the PS2 19 1 Features Conforms to PS...

Page 614: ...upt KTI interrupt KCLK PS2AC PS2BC PS2CC PS2DC Legend KD PS2 data I O pin KCLK PS2 clock I O pin KBBR Keyboard data buffer register KBCRH Keyboard control register H KBCRL Keyboard control register L...

Page 615: ...ion Channel Name Abbreviation I O Function PS2 clock I O pin KCLK0 PS2AC I O PS2 clock input output 0 PS2 data I O pin KD0 PS2AD I O PS2 data input output PS2 clock I O pin KCLK1 PS2BC I O PS2 clock i...

Page 616: ...Keyboard buffer transmit data register_1 KBTR_1 R W H FF H FEC3 8 Keyboard control register H_1 KBCRH_1 R W H 70 H FEDC 8 Keyboard control register L_1 KBCRL_1 R W H 70 H FEDD 8 Channel 1 Keyboard da...

Page 617: ...eared to 0 1 Starts data transmission Setting condition When 1 is written after reading the KBTS 0 6 PS 0 R W Transmit Parity Selection Selects even or odd parity 0 Selects odd parity 1 Selects even p...

Page 618: ...not be set when software standby mode or watch mode is cancelled However internal flag is set 1 KBTE 0 R W Transmit Completion Flag Indicates that data transmission is completed When KTIE and KBTE are...

Page 619: ...tial Value R W Description 7 to 4 All 1 R W Reserved These bits are always read as 0 The initial value should not be changed 3 2 1 0 TXCR3 TXCR2 TXCR1 TXCR0 0 0 0 0 R R R R Transmit Counter Indicates...

Page 620: ...Clock In Monitors the KCLK I O pin This bit cannot be modified 0 KCLK I O pin is low 1 KCLK I O pin is high 5 KDI 1 R Keyboard Data In Monitors the KDI I O pin This bit cannot be modified 0 KD I O pi...

Page 621: ...ite 0 in KBF 1 Setting conditions When data has been received normally and has been transferred to KBBR while KBFSEL 1 keyboard buffer register full flag When a KCLK falling edge is detected while KBF...

Page 622: ...eceive data into KBBR 0 Loading of receive data into KBBR is disabled 1 Loading of receive data into KBBR is enabled 6 KCLKO 1 R W Keyboard Clock Out Controls PS2 clock I O pin output 0 PS2 clock I O...

Page 623: ...R Receive Counter These bits indicate the received data bit Their value is incremented on the fall of KCLK These bits cannot be modified The receive counter is initialized by a reset and when 0 is wr...

Page 624: ...KB6 KB5 KB4 KB3 KB2 KB1 KB0 0 0 0 0 0 0 0 0 R R R R R R R R Keyboard Data 7 to 0 8 bit read only data Initialized to H 00 by a reset or when KBIOE is cleared to 0 19 3 6 Keyboard Buffer Transmit Data...

Page 625: ...Clear KBF flag receive enabled state Keyboard side in data transmission state Execute receive abort processing Error handling 1 Set the KBIOE bit to 1 in KBCRL 2 Read KBCRH and if the KCLKI and KDI bi...

Page 626: ...EJ09B0452 0100 1 2 3 KCLK pin state KD pin state KCLK input KCLK output KB7 to KB0 PER KBS KBF Start bit Parity bit Stop bit Receive processing error handling Automatic I O inhibit Previous data Recei...

Page 627: ...the transmit enabled state Write 1 to the KCLKO bit to clear the I O inhibit Check D0 to D7 the parity bit the stop bit and receive completion notification send data at the falling edge of the KCLK s...

Page 628: ...device connected to it keyboard side in the event of a protocol error etc In this case the system holds the clock low During reception the keyboard also outputs a clock for synchronization and the clo...

Page 629: ...ve operation 1 Read KBCRL and if KBF 1 perform processing 1 2 Read KBCRH and if the value of bits RXCR3 to RXCR0 is less than B 1001 write 0 in KCLKO to abort reception 3 If the value of bits RXCR3 to...

Page 630: ...state If there is transmit data the data is transmitted Figure 19 7 Sample Receive Abort Processing Flowchart 2 Keyboard side monitors clock during receive operation transmit operation as seen from ke...

Page 631: ...uency divided by N for medium speed mode KCLK KD pin state KCLKI KDI register Internal data bus read data Figure 19 9 KCLKI and KDI Read Timing 19 4 5 KCLKO and KDO Write Timing Figure 19 10 shows the...

Page 632: ...igure 19 11 shows the KBF setting timing and the KCLK pin states Note here indicates the clock signal frequency divided by N for medium speed mode KCLK pin Internal KCLK Falling edge signal RXCR3 to R...

Page 633: ...ided by N for medium speed mode Figure 19 12 Receive Counter and KBBR Data Load Timing 19 4 8 Operation during Data Reception If the KBS bit in KBCRH is set to 1 with other keyboard buffer control uni...

Page 634: ...t KBIOE KBF 1 interrupt generated KBE 0 KBBR reception disabled Interrupt handling Clear KBF KCLK pin fall detected KBFSEL 0 KBIE 1 KCLK falling edge interrupts enabled Yes No KCLK pin state KBF bit I...

Page 635: ...1 the KCIF is set after the first falling edge of KCLK has been detected At this time if KCIE is set to 1 the CPU is requested an interrupt KCIF is set at the same time when the TXCR3 to TXCR0 bits in...

Page 636: ...ing by an interrupt handing routine and then request retransfer When transition to software standby mode or watch mode is made and the mode is canceled by a first KCLK falling interrupt during data tr...

Page 637: ...nterrupt internal signal Interrupt generated a Interrupt timing in software standby mode and watch mode Software standby mode and watch mode internal signal KCLK 4 5 6 Interrupt internal signal Interr...

Page 638: ...008 Page 612 of 994 REJ09B0452 0100 First KCLK falling edge Internal flag KCLK Interrupt accepted Accepted at any timing 1 2 3 Interrupt generated Automatic clear Figure 19 18 Internal Flag of First K...

Page 639: ...at 1 Therefore if the KCLK pin is low when the KBIOE bit is set to 1 the edge detection circuit operates and the KCLK falling edge is detected If the KBFSEL bit and KBE bit are both 0 at this time the...

Page 640: ...gure 19 20 KDO Output 19 5 3 Module Stop Mode Setting Keyboard buffer control unit operation can be enabled or disabled using the module stop control register The initial setting is for keyboard buffe...

Page 641: ...me LFRAME Four register sets comprising data and status registers The basic register set comprises three bytes an input register IDR output register ODR and status register STR I O addresses from H 00...

Page 642: ...l conversion Address match SYNC output Parallel serial conversion Control logic Internal interrupt control Legend HICR0 to HICR5 LADR1H L to 4H L SCIFADRH L IDR1 to IDR4 ODR1 to ODR4 TWR1 to TWR15 TWR...

Page 643: ...ialized interrupt request SERIRQ P37 I O 1 Serialized host interrupt request signal in synchronization with LCLK LSCI general output LSCI PB1 Output 1 2 General output LSMI general output LSMI PB0 Out...

Page 644: ...H FDC1 8 LPC channel 2 address register H LADR2H R W H 00 H FDC2 8 LPC channel 2 address register L LADR2L R W H 62 H FDC3 8 LPC channel 3 address register H LADR3H R W H 00 H FE34 8 LPC channel 3 add...

Page 645: ...register 9 TWR9 R W R W H 00 H FE29 8 Bidirectional data register 10 TWR10 R W R W H 00 H FE2A 8 Bidirectional data register 11 TWR11 R W R W H 00 H FE2B 8 Bidirectional data register 12 TWR12 R W R W...

Page 646: ...W LPC Enables 3 to 1 Enable or disable the LPC interface function When the LPC interface is enabled one of the three bits is set to 1 processing for data transfer between the slave this LSI and the h...

Page 647: ...1 Fast Gate A20 function enabled GA20 pin output is open drain external pull up resistor Vcc required 3 SDWNE 0 R W LPC Software Shutdown Enable Controls LPC interface shutdown For details of the LPC...

Page 648: ...put Enable Controls LSMI output in combination with the LSMIB bit in HICR1 LSMI pin output is open drain and an external pull up resistor Vcc is needed LSMIE LSMIB 0 X LSMI output disabled other funct...

Page 649: ...Forced termination abort of transfer cycle subject to processing Normal termination of transfer cycle subject to processing 1 LPC interface is performing transfer cycle processing Setting condition Ma...

Page 650: ...e reset or LPC software reset LPC hardware shutdown or LPC software shutdown End of SERIRQ transfer frame 1 SERIRQ transfer processing in progress Setting condition Start of SERIRQ transfer frame 4 LR...

Page 651: ...eset LPC hardware shutdown falling edge of LPCPD signal when SDWNE 1 LPC hardware shutdown release rising edge of LPCPD signal when SDWNE 0 1 LPC software shutdown state Setting condition Writing 1 af...

Page 652: ...ating state of the functions that use pin multiplexing HICR2 R W Bit Bit Name Initial Value Slave Host Description 7 GA20 Undefined R GA20 Pin Monitor 6 LRST 0 R W LPC Reset Interrupt Flag This bit is...

Page 653: ...etting condition LFRAME pin falling edge detection during LPC transfer cycle 3 IBFIE3 0 R W IDR3 and TWR Receive Complete interrupt Enable Enables or disables IBFI3 interrupt to the slave this LSI 0 I...

Page 654: ...0 ERRIE 0 R W Error Interrupt Enable Enables or disables ERRI interrupt to the slave this LSI 0 Error interrupt requests disabled 1 Error interrupt requests enabled Note Only 0 can be written to bits...

Page 655: ...d The initial value bit should not be changed 6 LPC4E 0 R W LPC Enable 4 0 LPC channel 4 is disabled For IDR4 ODR4 and STR4 address LADR4 match is not occurred 1 LPC channel 4 enabled 5 IBFIE4 0 R W I...

Page 656: ...pt request is disabled 1 Output buffer empty interrupt request is enabled 6 OBEI 0 R W Output Buffer Empty Interrupt Flag 0 Clearing conditions Writing 0 after reading OBEI 1 LPC hardware reset or LPC...

Page 657: ...5 4 3 2 1 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W Channel 1 Address Bits 15 to 8 Set the LPC channel 1 host address LADR1L R W Bit Bit N...

Page 658: ...1 1 Bits 1 and 0 in LADR1 I O read STR1 read Note When channel 1 is used the content of LADR1 must be set so that the addresses for channels 2 3 4 and SCIF are different 20 3 6 LPC Channel 2 Address R...

Page 659: ...W R W Channel 2 Address Bits 1 and 0 Set the LPC channel 2 host address Host select register I O Address Bits 5 to 3 Bit 2 Bits 1 and 0 Transfer Cycle Host Select Register Bits 15 to 3 in LADR2 0 Bit...

Page 660: ...11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W Channel 3 Address Bits 15 to 8 Set the LPC channel 3 host address LADR3L R W Bit Bit Name Initial Value Slave Host Description 7 6...

Page 661: ...o 0 are ignored Host select register I O Address Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Transfer Cycle Host Select Register Bit 4 Bit 3 0 Bit 1 0 I O write IDR3 write C D3 0 Bit 4 Bit 3 1 Bit 1 0 I O write IDR...

Page 662: ...5 4 3 2 1 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W Channel 4 Address Bits 15 to 8 Set the LPC channel 4 host address LADR4L R W Bit Bit...

Page 663: ...ng table Data transferred in an LPC I O write cycle is written to the selected register The value of bit 2 of the I O address is latched into the C D bit in STR to indicate whether the written informa...

Page 664: ...ng the status flags whether or not those writes were valid For the registers selected from the host according to the I O address see section 20 3 7 LPC Channel 3 Address Registers H and L LADR3H and L...

Page 665: ...t of input data register IDR1 is a command 2 DBU12 0 R W R Defined by User The user can use this bit as necessary 1 IBF1 0 R R Input Buffer Full This bit is an internal interrupt source to the slave t...

Page 666: ...nd 0 Content of input data register IDR2 is a data 1 Content of input data register IDR2 is a command 2 DBU22 0 R W R Defined by User The user can use this bit as necessary 1 IBF2 0 R R Input Buffer F...

Page 667: ...Output Buffer Full Flag 0 Clearing conditions When the host reads TWR15 in I O read cycle When the slave writes 0 to the OBF3B bit 1 Setting condition When the slave writes to TWR15 5 MWMF 0 R R Maste...

Page 668: ...of input data register IDR3 is a command 2 DBU32 0 R W R Defined by User The user can use this bit as necessary 1 IBF3A 0 R R Input Buffer Full This bit is an internal interrupt source to the slave th...

Page 669: ...ta or a command 0 Content of input data register IDR3 is a data 1 Content of input data register IDR3 is a command 2 DBU32 0 R W R Defined by User The user can use this bit as necessary 1 IBF3 0 R R I...

Page 670: ...mmand 0 Content of input data register IDR4 is a data 1 Content of input data register IDR4 is a command 2 DBU42 0 R W R Defined by User The user can use this bit as necessary 1 IBF4 0 R R Input Buffe...

Page 671: ...Setting condition Specification by SERIRQ transfer cycle stop frame 6 SELREQ 0 R W Start Frame Initiation Request Select Selects the condition of a start frame initiation request when a host interrup...

Page 672: ...1 When IEDIR3 0 Host SMI interrupt request by setting OBF3B to 1 is enabled When IEDIR3 1 Host SMI interrupt is requested Setting condition Writing 1 after reading SMIE3B 0 3 SMIE3A 0 R W Host SMI In...

Page 673: ...aring OBF2 to 0 when IEDIR2 0 1 When IEDIR2 0 Host SMI interrupt request by setting OBF2 to 1 is enabled When IEDIR2 1 Host SMI interrupt is requested Setting condition Writing 1 after reading SMIE2 0...

Page 674: ...errupt Enable 1 Enables or disables a host HIRQ1 interrupt request when OBF1 is set by an ODR1 write 0 HIRQ1 interrupt request by OBF1 and IRQ1E1 is disabled Clearing conditions Writing 0 to IRQ1E1 LP...

Page 675: ...11E3 LPC hardware reset LPC software reset Clearing OBF3A to 0 when IEDIR3 0 1 When IEDIR3 0 HIRQ11 interrupt request by setting OBF3A to 1 is enabled When IEDIR3 1 HIRQ11 interrupt is requested Setti...

Page 676: ...1 When IEDIR3 0 HIRQ9 interrupt request by setting OBF3A to 1 is enabled When IEDIR3 1 HIRQ9 interrupt is requested Setting condition Writing 1 after reading IRQ9E3 0 4 IRQ6E3 0 R W Host IRQ6 Interru...

Page 677: ...When IEDIR2 0 HIRQ11 interrupt request by setting OBF2 to 1 is enabled When IEDIR2 1 HIRQ11 interrupt is requested Setting condition Writing 1 after reading IRQ11E2 0 2 IRQ10E2 0 R W Host IRQ10 Inter...

Page 678: ...0 1 When IEDIR2 0 HIRQ9 interrupt request by setting OBF2 to 1 is enabled When IEDIR2 1 HIRQ9 interrupt is requested Setting condition Writing 1 after reading IRQ9E2 0 0 IRQ6E2 0 R W Host IRQ6 Interru...

Page 679: ...affected only by a host interrupt enable bit or by an OBF flag in addition to the enable bit 0 A host interrupt is generated when both the enable bit and the corresponding OBF flag are set 1 A host in...

Page 680: ...When IEDIR4 0 HIRQ11 interrupt request by setting OBF4 to 1 is enabled When IEDIR4 1 HIRQ11 interrupt is requested Setting condition Writing 1 after reading IRQ11E4 0 4 IRQ10E4 0 R W Host IRQ10 Inter...

Page 681: ...0 1 When IEDIR4 0 HIRQ9 interrupt request by setting OBF4 to 1 is enabled When IEDIR4 1 HIRQ9 interrupt is requested Setting condition Writing 1 after reading IRQ9E4 0 2 IRQ6E4 0 R W Host IRQ6 Interru...

Page 682: ...nterrupt request by setting OBF4 to 1 is enabled When IEDIR4 1 Host SMI interrupt is requested Setting condition Writing 1 after reading SMIE4 0 0 0 R W Reserved The initial value should not be change...

Page 683: ...ave Host Description 7 to 4 All 0 R W Reserved The initial value should not be changed 3 2 1 0 SCSIRQ3 SCSIRQ2 SCSIRQ1 SCSIRQ0 0 0 0 0 R W R W R W R W SCIF SERIRQ Request These bits select host interr...

Page 684: ...H R W Bit Bit Name Initial Value Slave Host Description 7 0 R W 6 0 R W 5 0 R W 4 0 R W 3 0 R W 2 0 R W 1 1 R W 0 1 R W SCIF Addresses 15 to 8 These bits set the host addresses of the SCIF SCIFADRL R...

Page 685: ...s 7 to 4 in STR3 indicate processing status of the LPC interface 1 When TWRE 1 Bits 7 to 4 in STR3 indicate processing status of the LPC interface When TWRE 0 Bits 7 to 4 in STR3 are readable writable...

Page 686: ...interface after a reset release 1 Read the signal line status and confirm that the LPC module can be connected Also check that the LPC module is initialized internally 2 When using channels 1 2 and 4...

Page 687: ...t of the LPC transfer cycle has been requested In an I O read cycle or I O write cycle transfer is carried out using LAD3 to LAD0 in the following order in synchronization with LCLK The host can be ma...

Page 688: ...t Bits 15 to 12 4 Address 2 Host Bits 11 to 8 Address 2 Host Bits 11 to 8 5 Address 3 Host Bits 7 to 4 Address 3 Host Bits 7 to 4 6 Address 4 Host Bits 3 to 0 Address 4 Host Bits 3 to 0 7 Turnaround r...

Page 689: ...AD0 Number of clocks LCLK TAR Sync Data TAR Start Cycle type direction and size 1 1 4 1 2 2 2 1 Figure 20 2 Typical LFRAME Timing ADDR Start LFRAME LAD3 to LAD0 LCLK TAR Sync Cycle type direction and...

Page 690: ...ommand and outputs it on pin GA20 2 Fast Gate A20 Operation The internal state of pin GA20 is initialized to 1 since the initial value of the FGA20E bit is 0 When the FGA20E bit is set to 1 pin P81 GA...

Page 691: ...etting Condition Clearing Condition GA20 When bit 1 of the data that follows an H D1 host command is 1 When bit 1 of the data that follows an H D1 host command is 0 Start Wait for next byte H D1 comma...

Page 692: ...sequence 1 H D1 command 0 Q 0 1 data 1 0 1 1 0 Command other than H FF and H D1 1 Q 1 Turn on sequence abbreviated form 1 H D1 command 0 Q 0 0 data 2 0 0 1 0 Command other than H FF and H D1 1 Q 0 Tu...

Page 693: ...ware shutdown state is set by means of the SDWNB bit on the other hand the LPC software shutdown state cannot be cleared at the same time as the rising edge of the LPCPD signal Taking these points int...

Page 694: ...t Needed to clear shutdown state Legend O Pin that is shutdown by the shutdown function Pin that is shutdown only when the LPC function is selected by register setting X Pin that is not shutdown In th...

Page 695: ...be set cleared Can be set cleared SDWN flag Initialized 0 Initialized 0 Can be set cleared LRSTB bit Initialized 0 HR 0 SR 1 0 can be set SDWNB bit Initialized 0 Initialized 0 HS 0 SS 1 SDWNE bit Init...

Page 696: ...0 Apr 28 2008 Page 670 of 994 REJ09B0452 0100 Figure 20 5 shows the timing of the LPCPD and LRESET signals LPCPD LRESET LAD3 to LAD0 LFRAME LCLK At least 30 s At least 100 s At least 60 s Figure 20 5...

Page 697: ...Q Drive source LCLK START Start frame IRQ0 frame IRQ1 frame IRQ2 frame SL or H H R T R S T R S T R S T IRQ15 Host controller None None SERIRQ Driver LCLK START STOP IOCHCK frame Stop frame Next cycle...

Page 698: ...ve 3 Drive possible in SCIF 6 IRQ5 Slave 3 Drive possible in SCIF 7 IRQ6 Slave 3 Drive possible in LPC channels 2 3 4 and SCIF 8 IRQ7 Slave 3 Drive possible in SCIF 9 IRQ8 Slave 3 Drive possible in SC...

Page 699: ...lock Start Request 20 4 6 LPC Interface Clock Start Request A request to restart the clock LCLK can be sent to the host by means of the CLKRUN pin With LPC data transfer and SERIRQ in continuous mode...

Page 700: ...UI interrupts are command receive complete interrupts OBEI is an output buffer empty interrupt An interrupt request is enabled by setting the corresponding enable bit Table 20 9 Receive Complete Inter...

Page 701: ...ead of ODR or TWR15 by the host in the corresponding LPC channel the corresponding host interrupt enable bit is automatically cleared to 0 and the host interrupt request is cleared When the IEDIR bit...

Page 702: ...t reads ODR3 writes 0 to bit SMIE3B or host reads TWR15 writes 0 to bit SMIE4 or host reads ODR4 SMI IEDIR2 1 IEDIR3 1 or IEDIR4 1 Internal CPU reads 0 from bit SMIE2 then writes 1 reads 0 from bit SM...

Page 703: ...esponding SERIRQ host interrupt request for the SCIF in SIRQCR4 for details see the description of SIRQCR4 Changes in the SCIF input signal DCD are detected Reads FMSR and clears the DDCD bit in FMSR...

Page 704: ...R at the same time the data will be corrupted To prevent simultaneous accesses IBF and OBF must be used to allow access only to data for which writing has finished Unlike the IDR and ODR registers the...

Page 705: ...nd H A24E H 3FD0 and H 3FD4 ODR3 H A24A H 3FD0 STR3 H A24E H 3FD4 TWR0MW H A250 H 3FC0 TWR0SW H A250 H 3FC0 TWR1 H A251 H 3FC1 TWR2 H A252 H 3FC2 TWR3 H A253 H 3FC3 TWR4 H A254 H 3FC4 TWR5 H A255 H 3F...

Page 706: ...Section 20 LPC Interface LPC Rev 1 00 Apr 28 2008 Page 680 of 994 REJ09B0452 0100...

Page 707: ...ions between this LSI and SPI flash memory Can operate as a master Transfer clock selectable from system clock or LCLK Four interrupt sources Transmit end receive data full and command and write recei...

Page 708: ...SIWI SLCR LCLK LAD 3 to 0 LFRAME FSIHBARH L FSISR CMDHBRH L LPC I F Address Change FSILSTR1 2 FSIGPR1 to F FSIARLH M L FSIWDHH HL LH LL FSICMDR FSIRDINS FSIPPINS FSITEI FSIRXI Trans Rev Controller FSI...

Page 709: ...output FSIDO Output FSI address direction data output signal For details on the input output pins of the LPC interface see section 20 2 Input Output Pins Table 21 2 shows the initial state of the FSI...

Page 710: ...C98 FSI transmit data register 1 FSITDR1 R W H 00 H FC99 FSI transmit data register 2 FSITDR2 R W H 00 H FC9A FSI transmit data register 3 FSITDR3 R W H 00 H FC9B FSI transmit data register 4 FSITDR4...

Page 711: ...PRB R W R H 00 H FC61 FSI general purpose register C FSIGPRC R W R H 00 H FC62 FSI general purpose register D FSIGPRD R W R H 00 H FC63 FSI general purpose register E FSIGPRE R W R H 00 H FC64 FSI gen...

Page 712: ...is bit generates a clear signal for the sequencer in the corresponding module resulting in the initialization of the FSI s internal state 6 FSIE 0 R W FSI Enable 0 Disables FSI operation 1 Enables FSI...

Page 713: ...CPHS CPOS 0 0 Initial value of FSICK Low level Data changes at the FSICK falling edge 1 1 Initial value of FSICK High level Data changes at the FSICK falling edge 0 1 Setting prohibited 1 0 Setting p...

Page 714: ...completed 1 When LFBUSY 0 Starts transmission When LFBUSY 1 FSI transmission is in progress automatically set 6 RE 0 R W FSI Reception Enable Controls FSI reception and indicates reception status in c...

Page 715: ...f data bytes to be transmitted The TBN value is decremented each time one byte of FSI data transmission is completed When the FSI transmission ends TBN is cleared to B 0000 0000 Transmits no data 0001...

Page 716: ...one byte of data 010 Receives two bytes of data 011 Receives three bytes of data 100 Receives four bytes of data 101 to 111 Setting prohibited If reception of five bytes or more is specified FSIRDR is...

Page 717: ...S sets a program operation instruction to be sent to FSITDR during program operation When LFBUSY is set to 1 a write to this register by the EC this LSI is invalid This register should be modified dur...

Page 718: ...a Setting condition When the TE bit is set to 1 5 FSIRXI 0 R FSI Receive End Interrupt Flag Indicates whether or not there is data to be read by the EC this LSI 0 There is no read data Clearing condit...

Page 719: ...than FSICMDI and FSIWI interrupt processing R W Bit Bit Name Initial Value EC Host Description 7 to 0 bit 7 to bit 0 All 0 R W These bits store transmit data 21 3 9 FSI Receive Data Register FSIRDR F...

Page 720: ...peration in the state where FSIE or FSILIE is set do not change the setting in this register FSIHBARH R W Bit Bit Name Initial Value EC Host Description 7 to 0 bit 31 to bit 24 All 0 R W These bits sp...

Page 721: ...command address The lower 16 bits of the host start address range from H F000 to H F00F If a host address to be input to CMDHBARH and CMDHBARL is out of the determined range Sync will not be returned...

Page 722: ...ommand Status Register 1 FSILSTR1 FSILSTR1 indicates the LPC internal status R W Bit Bit Name Initial Value EC Host Description 7 CMDBUSY 0 R W R FSI Command Busy Flag 0 The FSI command execution is c...

Page 723: ...ansferring Setting condition SPI flash memory write is received when FLDCT 0 3 FSIWI 0 R W R FSI Write Interrupt Flag 0 FSI write interrupt is completed Clearing condition Read FSIWI 1 and then write...

Page 724: ...lag Indicates a FSI read transfer status during LPC SPI direct transfer 0 FSI read transfer is completed 1 During FSI read transfer 2 to 0 SIZE2 SIZE1 SIZE0 0 0 1 R R R Transfer Byte Count Monitor Ind...

Page 725: ...bles the LPC host interface function of the FSI FSI interrupt enable bit and FSI operation mode control bit R W Bit Bit Name Initial Value EC Host Description 7 FSILIE 0 R W FSI LPC Interface Enable E...

Page 726: ...e Operation Mode 0 No wait cycle is inserted 1 Wait cycles can be inserted 2 to 0 All 0 R W Reserved The initial value should not be modified 21 3 18 FSI Address Registers H M and L FSIARH FSIARM and...

Page 727: ...SIWDR stores data to be written to the SPI flash memory If the host address matches FSIHBAR during LPC FW memory write cycle the FSIWDR value will be updated FSIHBAR value is not updated by command ac...

Page 728: ...Bit Bit Name Initial Value EC Host Description 7 to 0 bit 15 to bit 8 All 0 R These bits store bits 15 8 of the SPI flash memory write data FSIWDRLL R W Bit Bit Name Initial Value EC Host Description...

Page 729: ...Write Cycles LPC Memory Read Cycles LPC Memory Write Cycles State Counts Content Driven by Value 3 to 0 Content Driven by Value 3 to 0 1 Start Host 0000 Start Host 0000 2 Cycle type direction Host 01...

Page 730: ...Start Host 1101 Start Host 1110 2 Device select Host ID3 to ID0 Device select Host ID3 to ID0 3 Address 1 Host bit 27 to bit 24 Address 1 Host bit 27 to bit 24 4 Address 2 Host bit 23 to bit 20 Addres...

Page 731: ...read and write cycles In word transfer the least address bit is fixed to B 0 while in longword transfer the lower 2 bits are fixed to B 00 When longword transfers of FW memory write cycles are used th...

Page 732: ...R Reads status register WRSR Writes status register READ Reads SPI flash memory Fast Read Fast reads SPI flash memory Byte Program Byte programs SPI flash memory Page Program Page programs SPI flash m...

Page 733: ...n execution 1 FSI Address Conversion The host address can be converted into the SPI flash memory address by setting FSIHBARH FSIHBARL and FSISR The host address space ranges from H 0000_0000 to H FFFF...

Page 734: ...TDR After SYNC long wait has been returned the TE bit in FSICR2 is set starting the Byte Page Program instruction execution When the transmission has been completed SYNC Ready and TAR are returned to...

Page 735: ...LAD 3 0 ST CT ADDR DATA TAR WAIT SY TAR FSIAR 23 0 FSIWDR 31 0 FSIPPINS 7 0 FSICR2 TE bit FSITDR7 to FSITDR0 FSISTR OBF bit FSISS FSICK CPOS CPHS 0 FSIDO H 06 4A 70 H 67 45 23 01 H 67 45 23 01 70 4A 0...

Page 736: ...g bytes an instruction and data in this order are transmitted to the SPI flash memory When the transmission has been completed SYNC Ready and TAR are returned to the host To execute the AAI Program in...

Page 737: ...cycle occurs while the FRDE bit in FSICR1 is cleared to 0 the SPI flash memory address is stored in FSIAR Then the SPI flash memory address and the instruction which is stored in FSIRDINS in advance a...

Page 738: ...IAR 7 0 FSIAR 15 8 FSIAR 23 16 H 67_45_23_01 H 06_4A_70 H 03 FSIAR 23 0 FSIRDINS 7 0 FSISFR FSIDI FSIDO Figure 21 8 Data Transfer to FSIRDR Example LCLK LFRAME LAD 3 0 ST CT ADDR DATA TAR WAIT SY TAR...

Page 739: ...bit in FSICR2 is set and Fast Read instruction execution starts The read data is then received and stored in FSIRDR When the reception has been completed SYNC Ready read data and TAR are returned to t...

Page 740: ...n be used as FSI command space according to the CMDHBAR settings Figure 21 11 shows an example of FSI command space settings Host addresses FSI command area H EFFF_0000 H EFFF_F000 H EFFF_F00F H EFFF_...

Page 741: ...host address are set to the value in the CMDHBAR register Figure 21 12 FSI Command Write Operation Example As shown in figure 21 12 if a host address ranging from H EFFF_F000 to H EFFF_F00F is access...

Page 742: ...to the value in the CMDHBAR register Figure 21 13 FSI Command Read Example As shown in figure 21 13 if a host address ranging from H EFFF_F000 to H EFFF_F00F is accessed in LPC FW memory read cycle wh...

Page 743: ...IWDR 31 0 FSIAR 23 0 B 1 H 0000_0073 H 06_4A76 FSIDMYE FSIWDR 31 0 FSIAR 23 0 B 0 H 0000_00D4 H 0F_1BC3 Byte Program H 232E_1BC3 H D4 H D4 SPI Flash memory H 0F_1BC3 Flash memory address Figure 21 14...

Page 744: ...ommand data H 10 FSICMDR 7 0 Command data H 11 FSICMDI B 0 B 1 FSICMDI B 0 B 1 B 0 B 1 B 1 B 1 FSIDMDIE B 1 FSICMDIE FSIDMYE FSIDMYE B 1 FSIDMYE Interrupt requests Interrupt requests FSIAR 23 0 H 06_4...

Page 745: ...cution Timing of SPI Flash Memory Step 1 1 Write an erasure setting command Host 2 Generate an FSICMDI interrupt request 3 Set the FSIDMYE bit in FSILSTR1 to 1 and clear the FSICMDI and CMDBUSY bits i...

Page 746: ...t the FSIDMYE CMDBUSY and FSICMDI bits in FSILSTR1 are cleared to 0 Host 6 FSI Command Usage Example 2 SPI Flash Memory Status Read Figure 21 17 shows an example of the execution timing of the SPI fla...

Page 747: ...struction Set the RE bit in FSICR2 to 1 Set the TBN bit in FSIBNR to 1 byte transfer and set the RBN bit in FSIBNR to 1 byte reception Write the status read instruction to FSIINS start the SPI flash m...

Page 748: ...o wait cycle is inserted to the LPC bus Confirm by FSIWBUSY whether or not a write transfer has been completed Mode 2 0 1 FSIWBUSY 1 FSIWI 1 Control the write operation to the SPI flash memory by the...

Page 749: ...d Retained Retained Retained Retained FSILSTR1 Bits 7 6 4 and 3 Initialized Initialized Retained Retained Initialized Bits 5 and 2 to 0 Initialized Retained Retained Retained Retained FSILSTR2 Bits 7...

Page 750: ...2 to 0 Initialized Retained Retained Retained Initialized FSIINS Bits 7 to 0 Initialized Retained Retained Retained Retained FSIRDINS Bits 7 to 0 Initialized Retained Retained Retained Retained FSIPP...

Page 751: ...FSI command write FSIWI is a write receive interrupt in the case of write from the host to the SPI flash memory Setting the corresponding enable bit to 1 enables the relevant interrupt request to be...

Page 752: ...Section 21 FSI Interface Rev 1 00 Apr 28 2008 Page 726 of 994 REJ09B0452 0100...

Page 753: ...cle 40 cycles A D conversion clock Two kinds of operating modes Single mode Single channel A D conversion Scan mode Continuous A D conversion on one to four channels or continuous A D conversion on on...

Page 754: ...ster E A D data register F A D data register G A D data register H Conversion start trigger from TPU or 8 bit timer 8 2 4 Module data bus Control circuit Internal data bus 10 bit D A Comparator Sample...

Page 755: ...ame Symbol I O Function Analog power supply pin AVCC Input Analog block power supply Analog ground pin AVSS Input Analog block ground Reference power supply pin AVref Input Reference voltage for A D c...

Page 756: ...D data register A ADDRA R H 0000 H FC00 16 A D data register B ADDRB R H 0000 H FC02 16 A D data register C ADDRC R H 0000 H FC04 16 A D data register D ADDRD R H 0000 H FC06 16 A D data register E A...

Page 757: ...ata is stored in bits 15 to 6 The lower six bits are always read as 0 The data bus between the CPU and the A D converter is sixteen bits wide The data can be read directly from the CPU ADDR must not b...

Page 758: ...er reading ADF 1 6 ADIE 0 R W A D Interrupt Enable Enables ADI interrupt by ADF when this bit is set to 1 5 ADST 0 R W A D Start When this bit is cleared to 0 A D conversion stops and enters wait stat...

Page 759: ...9 1010 AN10 1011 AN11 1100 AN12 1101 AN13 1110 AN14 1111 AN15 When SCANE 1 and SCANS 0 0000 AN0 0001 AN0 AN1 0010 AN0 to AN2 0011 AN0 to AN3 0100 AN4 0101 AN4 AN5 0110 AN4 to AN6 0111 AN4 to AN7 1000...

Page 760: ...Mode Select the A D conversion operating mode 0X Single mode 10 Scan mode Continuous A D conversion on 1 to 4 channels 11 Scan mode Continuous A D conversion on 1 to 8 channels 3 2 CKS1 CKS0 0 0 R W...

Page 761: ...nversion is to be performed only once on the specified single channel Operations are as follows 1 A D conversion on the specified channel is started when the ADST bit in ADCSR is set to 1 by software...

Page 762: ...nnels is selected A D conversion starts from the following channels AN0 when CH3 0 and CH2 0 and AN8 when CH3 1 and CH2 0 3 When A D conversion for each channel is completed the result is sequentially...

Page 763: ...put sampling time tSPL The length of tD varies depending on the timing of write to ADCSR The total conversion time therefore varies within the ranges indicated in table 22 4 In scan mode the values sh...

Page 764: ...in Typ Max Min Typ Max Min Typ Max Min Typ Max A D conversion start delay time tD 4 5 6 9 10 17 18 33 Input sampling time tSPL 15 30 60 120 A D conversion time tCONV 44 45 8x 8x 16x 16x 32x 32x Note V...

Page 765: ...by 1 2 LSB see figure 22 3 Offset error The deviation of the analog input voltage value from the ideal A D conversion characteristics when the digital output changes from the minimum voltage value B...

Page 766: ...1024 FS Quantization error Digital output Ideal A D conversion characteristic Analog input voltage Figure 22 3 A D Conversion Accuracy Definitions FS Digital output Ideal A D conversion characteristic...

Page 767: ...charged within the sampling time if the sensor output impedance exceeds 5 k charging may be insufficient and it may not be possible to guarantee the A D conversion accuracy However if a large capacita...

Page 768: ...ation between AVcc AVss and Vcc Vss As the relationship between AVcc AVss and Vcc Vss set AVcc Vcc 0 3 V and AVss Vss If the A D converter is not used set AVcc Vcc and AVss Vss AVref pin range The ref...

Page 769: ...nected to AVss If a filter capacitor is connected the input currents at the analog input pins AN0 to AN15 are averaged and so an error may arise Also when A D conversion is performed frequently as in...

Page 770: ...e Values are reference values Figure 22 7 Analog Input Pin Equivalent Circuit 22 7 7 Module Stop Mode Setting When this LSI enters software standby mode with A D conversion enabled the analog inputs a...

Page 771: ...etting changing the setting of the SCANE and ADSTCLR bits to switch from continuous scan mode to single mode or one cycle scan mode If any of the above points is applicable please make settings in acc...

Page 772: ...ate the external trigger ADCSR ADST 0 Change the scan mode change the extaernal trigger setting Note Overwrite the TRGS1 and TRGS0 bits settings at the same time in a byte unit Extaernal trigger shut...

Page 773: ...igh speed static RAM The RAM is connected to the CPU by a 16 bit data bus enabling one state access by the CPU for both byte data and word data The on chip RAM can be enabled or disabled by means of t...

Page 774: ...Section 23 RAM Rev 1 00 Apr 28 2008 Page 748 of 994 REJ09B0452 0100...

Page 775: ...ng time 1 ms typ for 128 byte simultaneous programming 7 8 s per byte Erasing time 600 ms typ per 1 block 64 kbytes Number of programming The number of programming can be up to 100 times at the minimu...

Page 776: ...Flash transfer destination address register Note To read write the registers above the FLSHE bit in the serial timer control register STCR must be set to 1 Figure 24 1 Block Diagram of Flash Memory 24...

Page 777: ...ming On board programming PROM programmer Programming erasing enable MAT User MAT User boot MAT User MAT User MAT User MAT User boot MAT All erasure O Automatic O O O Automatic Block division erasure...

Page 778: ...ween two MATs the MAT must be switched by using FMATS The user MAT or user boot MAT can be read in all modes However the user boot MAT can be programmed only in boot mode and programmer mode User MAT...

Page 779: ...H 003FFF H 01FFFF H 00607F H 006FFF H 00707F H 007FFF H 00807F H 00FFFF H 01007F Programming unit 128 bytes Programming unit 128 bytes Programming unit 128 bytes Programming unit 128 bytes Programmin...

Page 780: ...face parameters The procedure program for user program mode is made by the user Figure 24 5 shows the procedure for creating the procedure program For details see section 24 8 2 User Program Mode Down...

Page 781: ...firmed 3 Initialization of Programming Erasing A pulse with the specified period must be applied when programming or erasing The specified pulse width is made by the method in which wait loop is confi...

Page 782: ...ck number Since the downloaded on chip program is left in the on chip RAM even after programming erasing completes download and initialization are not required when the same processing is executed con...

Page 783: ...gister FTDAR R W H 00 H FEAE 8 Note Bits other than the SCO bit are read only bits The SCO bit is a write only bit and is always read as 0 Table 24 4 Parameter Configuration Register Name Abbreviation...

Page 784: ...n in table 24 5 Table 24 5 Registers Parameters and Target Modes Register Parameter Download Initiali zation Program ming Erasure Read FCCS O FPCS O FECS O FKEY O O O FMATS O 1 O 1 O 2 Programming era...

Page 785: ...or has occurred during programming or erasing the flash memory When this bit is set to 1 the flash memory enters the error protection state When this bit is set to 1 high voltage is applied to the int...

Page 786: ...eration must be executed in the on chip RAM Dummy read of FCCS must be executed twice immediately after setting this bit to 1 All interrupts must be disabled during download This bit is cleared to 0 w...

Page 787: ...ng program to be downloaded 0 Programming program is not selected Clearing condition When transfer is completed 1 Programming program is selected 3 Flash Erase Code Select Register FECS FECS selects t...

Page 788: ...it in FCCS is enabled When a value other than H A5 is written the SCO bit cannot be set to 1 Therefore the on chip program cannot be downloaded to the on chip RAM Only when H 5A is written can program...

Page 789: ...iting a value in FMATS To switch the MAT make sure to follow section 24 10 Switching between User MAT and User Boot MAT The user boot MAT cannot be programmed in user program mode even if the user boo...

Page 790: ...in FCCS to 1 Make sure that this bit is cleared to 0 before setting the SCO bit to 1 and the value specified by bits TDA6 to TDA0 should be within the range of H 00 to H 01 0 The value specified by b...

Page 791: ...erasing interface parameters are used in download control initialization before programming or erasing programming and erasing Table 24 6 shows the usable parameters and target modes The meaning of t...

Page 792: ...satisfy 128 bytes 128 byte program data is prepared by filling the dummy code H FF The boundary of the start address of the programming destination on the user MAT is aligned at an address where the...

Page 793: ...When the program to be downloaded is not selected more than two types of programs are selected or a program which is not mapped is selected an error occurs 0 Download program selection is normal 1 Do...

Page 794: ...ing FPFR indicates the return value of the initialization result Bit Bit Name Initial Value R W Description 7 to 2 Unused These bits return 0 1 FQ R W Frequency Error Detect Compares the specified CPU...

Page 795: ...ution Error Detect Writes 1 to this bit when the specified data could not be written because the user MAT was not erased If this bit is set to 1 there is a high possibility that the user MAT has been...

Page 796: ...destination for the program data is abnormal 1 WA R W Write Address Error Detect When the following items are specified as the start address of the programming destination an error occurs An area othe...

Page 797: ...EE R W Erasure Execution Error Detect Returns 1 when the user MAT could not be erased or when the flash memory related register settings are partially changed If this bit is set to 1 there is a high...

Page 798: ...Checks whether the specified erase block number is in the block range of the user MAT and returns the result 0 Setting of erase block number is normal 1 Setting of erase block number is abnormal 2 1...

Page 799: ...Frequency Set These bits set the operating frequency of the CPU The setting value must be calculated as follows 1 Round off the operating frequency expressed in MHz unit at the third decimal place to...

Page 800: ...cutive 128 byte programming is executed starting from the specified start address of the user MAT Therefore the specified start address of the programming destination becomes a 128 byte boundary and M...

Page 801: ...of 0 corresponds to block EB0 and a value of 10 corresponds to block EB10 Do not set a value outside the range from 0 to 10 Bit Bit Name Initial Value R W Description 31 to 8 Undefined R W Unused Thes...

Page 802: ...Boot mode 1 0 1 User program mode 0 1 0 1 User boot mode 1 0 0 24 8 1 Boot Mode Boot mode executes programming erasing of the user MAT and the user boot MAT by means of the control command and program...

Page 803: ...yte of H 00 to the host as the bit adjustment end sign When the host receives this bit adjustment end sign normally it transmits 1 byte of H 55 to this LSI When reception is not executed normally init...

Page 804: ...e H 00 H 00 reception H 00 transmission adjustment completed Bit rate adjustment Processing of inquiry setting command All user MAT and user boot MAT erasure Wait for program data Wait for erase block...

Page 805: ...ate of waiting for erase block data is entered The erase block number must be transmitted after the erasing command is transmitted When the erasure is finished the erase block number must be set to H...

Page 806: ...e during programming erasing may damage the flash memory If a reset is input the reset must be released after the reset input period period of RES 0 of at least 100 s When programming program data is...

Page 807: ...e on chip program and procedure program do not overlap Figure 24 11 shows the area of the on chip program to be downloaded H FFEFFF Programming programming end erasing program entry System use area 15...

Page 808: ...or processing Set the FPEFEQ parameter Yes End programming procedure program FPFR 0 No Disable interrupts and bus master operation other than CPU Clear FKEY to 0 Programming JSR FTDAR setting 16 Yes F...

Page 809: ...in the DPFR parameter The on chip RAM start address of the download destination is specified by FTDAR 2 Write H A5 in FKEY If H A5 is not written to FKEY the SCO bit in FCCS cannot be set to 1 to req...

Page 810: ...ively 5 The operating frequency of the CPU is set in the FPEFEQ parameter for initialization The settable operating frequency of the FPEFEQ parameter ranges from 8 to 32 MHz When the frequency is set...

Page 811: ...t address of the program data storage area FMPDR parameter is set in general register ER0 Example of FMPAR parameter setting When an address other than one in the user MAT area is specified for the st...

Page 812: ...in 128 byte units and repeat steps 11 to 14 Increment the programming destination address by 128 bytes and update the programming data pointer correctly If an address which has already been programmed...

Page 813: ...Yes Required block erasing is completed No Set FKEY to H 5A Clear FKEY to 0 1 2 3 4 5 6 Download Initialization Erasing Initialization JSR FTDAR setting 32 Erasing JSR FTDAR setting 16 Select on chip...

Page 814: ...ck number of the user MAT is set no block is erased even though the erasing program is executed and an error is returned to the FPFR parameter 3 Erasure is executed Similar to as in programming the en...

Page 815: ...s executed in user boot mode the built in check routine runs The user MAT and user boot MAT states are checked by this check routine While the check routine is running NMI and all other interrupts can...

Page 816: ...AT switchover MAT switchover DPFR 0 Initialization JSR FTDAR setting 32 Programming JSR FTDAR setting 16 FPFR 0 Select on chip program to be downloaded and specify download destination by FTDAR Note T...

Page 817: ...tween User MAT and User Boot MAT Except for MAT switching the programming procedure is the same as that in user program mode The area that can be executed in the steps of the user procedure program on...

Page 818: ...switchover MAT switchover DPFR 0 Initialization JSR FTDAR setting 32 Programming JSR FTDAR setting 16 FPFR 0 Select on chip program to be downloaded and specify download destination by FTDAR Note The...

Page 819: ...fore programming erasing starts download result is determined The flash memory is not accessible during programming erasing Programming erasing is executed by the program downloaded to the on chip RAM...

Page 820: ...MAT User MAT Embedded Program Storage MAT Storage area for program data O Operation for selecting on chip program to be downloaded O O O Operation for writing H A5 to FKEY O O O Execution of writing 1...

Page 821: ...CO bit in FCCS download O O Operation for clearing FKEY O O O Decision of download result O O O Operation for download error O O O Operation for setting initialization parameter O O O Execution of ini...

Page 822: ...clearing Determination of download result Download error processing Setting initialization parameter Initialization Determination of initialization result Initialization error processing NMI handling...

Page 823: ...ing 1 to SCO in FCCS download FKEY clearing Determination of download result Download error processing Setting initialization parameter Initialization Determination of initialization result Initializa...

Page 824: ...rogramming erasing is indicated by the FPFR parameter Table 24 14 Hardware Protection Function to be Protected Item Description Download Programming Erasing Reset protection The programming erasing in...

Page 825: ...are disabled unless the required key code is written in FKEY O O 24 9 3 Error Protection Error protection is a mechanism for aborting programming or erasure when a CPU runaway occurs or operations no...

Page 826: ...sed The state transition diagram in figure 24 16 shows transitions to and from the error protection state Reset hardware protection Programming erasing mode Error protection mode Error protection mode...

Page 827: ...no guarantee of which memory MAT is being accessed Always mask the maskable interrupts before switching between MATs In addition configure the system so that NMI interrupts do not occur during MAT swi...

Page 828: ...erface Specifications for Boot Mode The boot program initiated in boot mode performs serial communication using the host and on chip SCI_1 The serial communication interface specifications are shown b...

Page 829: ...m checks and blank checks are executed by sending these commands from the host These boot program states are shown in figure 24 18 Transition to programming erasing Programming erasing wait Checking I...

Page 830: ...55 H FF error Figure 24 19 Bit Rate Adjustment Sequence 2 Communications Protocol After adjustment of the bit rate the protocol for serial communications between the host and the boot program is as s...

Page 831: ...response Figure 24 20 Communication Protocol Format Command one byte Commands including inquiries selection programming erasing and checking Response one byte Response to an inquiry Size one byte The...

Page 832: ...er of frequency divided clock types the number of division ratios and the values of each division H 23 Operating clock frequency inquiry Inquiry regarding the maximum and minimum values of the main cl...

Page 833: ...and the product code in response to the supported device inquiry Command H 20 Command H 20 one byte Inquiry regarding supported devices Response H 30 Size Number of devices Number of characters Devic...

Page 834: ...when the device code matches Error response H 90 ERROR Error response H 90 one byte Error response to the device selection command ERROR one byte Error code H 11 Sum check error H 21 Device code error...

Page 835: ...unt of data that represents the modes Mode one byte A clock mode returned in reply to the supported clock mode inquiry SUM one byte Checksum Response H 06 Response H 06 one byte Response to the clock...

Page 836: ...tios Number of types one byte The number of supported divided clock types e g when there are two divided clock types which are the main and peripheral clocks the number of types will be H 02 Number of...

Page 837: ...and the number of frequencies Number of operating clock frequencies one byte The number of supported operating clock frequency types e g when there are two operating clock frequency types which are t...

Page 838: ...onse H 34 one byte Response to the user boot MAT information inquiry Size one byte The number of bytes that represents the number of areas area start address and area last address Number of areas one...

Page 839: ...er of areas is H 01 Area start address four bytes Start address of the area Area last address four bytes Last address of the area There are as many groups of data representing the start and last addre...

Page 840: ...he unit for reception of programming SUM one byte Checksum k New Bit Rate Selection The boot program will set a new bit rate and return the new bit rate This selection should be sent after sending the...

Page 841: ...r the peripheral frequency Division ratio The inverse of the division ratio as a negative number E g when the clock is divided by two the value of division ratio will be H FE H FE D 2 SUM one byte Che...

Page 842: ...Input frequency Division ratio The calculated operating frequency should be checked to ensure that it is within the range of minimum to maximum frequencies which are available with the clock modes of...

Page 843: ...r the programming erasing state The host should select the device code clock mode and new bit rate with device selection clock mode selection and new bit rate selection commands and then send the comm...

Page 844: ...should be made to inquire about the supported clock modes 4 The clock mode should be selected from among those described by the returned information and set 5 After selection of the device and clock m...

Page 845: ...programming selection Transfers the user boot MAT programming program H 43 User MAT programming selection Transfers the user MAT programming program H 50 128 byte programming Programs 128 bytes of da...

Page 846: ...byte commands should repeatedly be executed Sending a 128 byte programming command with H FFFFFFFF as the address will stop the programming On completion of programming the boot program will wait for...

Page 847: ...ecuted if two or more blocks are to be erased Sending a block erasure command from the host with the block number H FF will stop the erasure operating On completion of erasing the boot program will wa...

Page 848: ...yte Error response to user boot MAT programming selection ERROR 1 byte Error code H 54 Selection processing error transfer error occurs and processing is not completed b User MAT Programming Selection...

Page 849: ...onse H 06 one byte Response to 128 byte programming On completion of programming the boot program will return ACK Error Response H D0 ERROR Error response H D0 one byte Error response for 128 byte pro...

Page 850: ...r 128 byte programming ERROR one byte Error code H 11 Checksum error H 53 Programming error An error has occurred in programming and programming cannot be continued d Erasure Selection The boot progra...

Page 851: ...ROR Error Response H D8 one byte Response to Erasure ERROR one byte Error code H 11 Sum check error H 29 Block number error Block number is incorrect H 51 Erasure error An error has occurred during er...

Page 852: ...when the area setting is incorrect Read address 4 bytes Start address to be read from Read size 4 bytes Size of data to be read SUM 1 byte Checksum Response H 52 Read size Data SUM Response H 52 1 by...

Page 853: ...bytes Checksum of user boot MATs The total of the data is obtained in byte units SUM one byte Sum check for data being transmitted h User Program Sum Check The boot program will return the byte by by...

Page 854: ...sponse H CC H 52 Error Response H CC one byte Error response to the blank check of user boot MATs Error code H 52 one byte Erasure has not been completed j User MAT Blank Check The boot program will c...

Page 855: ...ogram state inquiry Size one byte The number of bytes This is fixed to 2 Status one byte State of the boot program ERROR one byte Error status ERROR 0 indicates normal operation ERROR 1 indicates erro...

Page 856: ...mismatch error H 22 Clock mode mismatch error H 24 Bit rate selection error H 25 Input frequency error H 26 Division ratio error H 27 Operating frequency error H 29 Block number error H 2A Address er...

Page 857: ...s finished secure the reset input period period of RES 0 of at least 100 s Transition to the reset state during programming erasing is inhibited If a reset is input accidentally the reset must be rele...

Page 858: ...sure to download the on chip program to execute programming erasing of the flash memory in this F ZTAT H8 H8S microcomputer 15 Unlike a conventional F ZTAT H8 H8S microcomputers measures against a pr...

Page 859: ...ulse generator EXTAL XTAL EXCL ExEXCL WDT_1 count clock CIR sampling clock SUB Subclock input circuit Subclock waveform forming circuit Oscillator System clock to pin Internal clock to on chip periphe...

Page 860: ...d An AT cut parallel resonance crystal resonator should be used Figure 25 3 shows an equivalent circuit of a crystal resonator A crystal resonator having the characteristics given in table 25 2 should...

Page 861: ...capacitance should be 10 pF or less To input an inverted clock to the XTAL pin the external clock should be set to high in standby mode or watch mode External clock input conditions are shown in tabl...

Page 862: ...c Figure 28 4 tEXH tEXL tEXr tEXf VCC 0 5 EXTAL Figure 25 5 External Clock Input Timing The oscillator and duty correction circuit can adjust the waveform of the external clock input that is input fro...

Page 863: ...to 3 6 V VSS AVSS 0 V Item Symbol Min Max Unit Remarks External clock output stabilization delay time tDEXT 500 s Figure 25 6 Note tDEXT includes a RES pulse width tRESW tDEXT RES Internal and extern...

Page 864: ...ring the DDR bit of the pin to 0 The EXCL pin is specified as an input pin by clearing the EXCLS bit in PTCNT0 to 0 The ExEXCL pin is specified as an input pin by setting the EXCLS bit in PTCNT0 to 1...

Page 865: ...not sampled in watch mode 25 5 Clock Select Circuit The clock select circuit selects the system clock that is used in this LSI A clock generated by the oscillator to which the XTAL and EXTAL pins are...

Page 866: ...the resonator circuit ratings that vary depending on the stray capacitances of the resonator and installation circuit Make sure the voltage applied to the oscillation pins do not exceed the maximum ra...

Page 867: ...op operating Module stop mode Independently of above operating modes on chip peripheral modules that are not used can be stopped individually 26 1 Register Descriptions Power down modes are controlled...

Page 868: ...h mode Note that the SSBY bit is not changed even if a mode transition is made by an interrupt 6 5 4 STS2 STS1 STS0 0 0 0 R W R W R W Standby Timer Select 2 to 0 On canceling software standby mode or...

Page 869: ...0 000 High speed mode 001 Medium speed clock 2 010 Medium speed clock 4 011 Medium speed clock 8 100 Medium speed clock 16 101 Medium speed clock 32 11X Setting prohibited Legend X Don t care Table 26...

Page 870: ...requency Select Selects the frequency by which the subclock SUB input from the EXCL or ExEXCL pin is sampled using the clock generated by the system clock pulse generator Clear this bit to 0 when is 5...

Page 871: ...ld not be changed 4 MSTP12 1 R W 8 bit timers TMR_0 and TMR_1 3 MSTP11 1 R W 14 bit PWM timer PWMX 2 MSTP10 1 R W Reserved The initial value should not be changed 1 MSTP9 1 R W A D converter 0 MSTP8 1...

Page 872: ...e should not be changed Note Before accessing registers of the FSI interface clear bit 0 in MSTPCRL MSTP0 and bit 2 in MSTPCRA MSTPA2 to 0 MSTPCRB Bit Bit Name Initial Value R W Corresponding Module 7...

Page 873: ...ets operation or stop by a combination of bits as follows MSTPCRH MSTP11 MSTPCRA MSTPA1 Function 0 0 14 bit PWM timer PWMX operates 0 1 14 bit PWM timer PWMX stops 1 0 14 bit PWM timer PWMX stops 1 1...

Page 874: ...LEEP instruction Any interrupt SLEEP instruction External interrupt 2 Interrupt 1 LSON bit 0 RES pin Low SSBY 0 LSON 0 SSBY 1 PSS 0 LSON 0 SSBY 1 PSS 1 DTON 0 RES pin High Transition after exception p...

Page 875: ...WDT_1 CIR Subclock operation WDT_0 Functioning TMR_0 TMR_1 TPU TCM_0 to 3 TDP_0 to 2 TMR_X TMR_Y SCIF IIC_0 to 2 LPC FSI Functioning PS2_0 to 3 Medium speed operation functioning Functioning stopped...

Page 876: ...of the current bus cycle by clearing all of bits SCK2 to SCK0 to 0 If the SLEEP instruction is executed when the SSBY bit in SBYCR is 0 and the LSON bit in LPWRCR is 0 a transition is made to sleep m...

Page 877: ...tandby mode the CPU on chip peripheral modules and clock pulse generator all stop However the contents of the CPU registers on chip RAM data I O ports and the states of on chip peripheral modules othe...

Page 878: ...s made to software standby mode at the falling edge of the NMI pin and software standby mode is cleared at the rising edge of the NMI pin In this example an NMI interrupt is accepted with the NMIEG bi...

Page 879: ...is made to high speed mode a stable clock is supplied to the entire LSI and interrupt exception handling starts after the time set in the STS2 to STS0 bits in SBYCR has elapsed In the case of an IRQ0...

Page 880: ...nal states of on chip peripheral modules other than the SCI PWM PWMX and A D converter are retained After the reset state is cancelled all on chip peripheral modules are in module stop mode While an o...

Page 881: ...ister addresses in section 27 1 Register Addresses Address Order Reserved bits are indicated by in the bit name column The bit number in the bit name column indicates that the whole register is alloca...

Page 882: ...data register P2DR 8 H F903 PORTS 1 PORT 8 2 Port 1 input data register P1PIN 8 H F904 Read PORTS 1 PORT 8 2 Port 2 input data register P2PIN 8 H F905 Read PORTS 1 PORT 8 2 Port 1 pull up MOS control...

Page 883: ...register P6NCE 8 H F92B PORTS 1 PORT 8 2 Port 6 noise canceler decision control register P6NCMC 8 H F92D PORTS 1 PORT 8 2 Port 6 noise cancel cycle setting register P6NCCS 8 H F92F PORTS 1 PORT 8 2 Po...

Page 884: ...2 Port D data direction register PDDDR 8 H F961 PORTS 1 PORT 8 2 Port C output data register PCODR 8 H F962 PORTS 1 PORT 8 2 Port D output data register PDODR 8 H F963 PORTS 1 PORT 8 2 Port C input da...

Page 885: ...ister PGDDR 8 H F980 PORTS 1 PORT 8 2 Port H data direction register PHDDR 8 H F981 PORTS 1 PORT 8 2 Port G output data register PGODR 8 H F982 PORTS 1 PORT 8 2 Port H output data register PHODR 8 H F...

Page 886: ...0 CIR 8 2 Receive control register 2 CCR2 8 H FA41 CIR 8 2 Receive status register CSTR 8 H FA42 CIR 8 2 Interrupt enable register CEIR 8 H FA43 CIR 8 2 Bit rate register BRR 8 H FA44 CIR 8 2 Receive...

Page 887: ...lower limit register_0 TDPPDMN_0 16 H FB50 TDP_0 16 2 TDP timer counter_1 TDPCNT_1 16 H FB60 TDP_1 16 2 TDP pulse width upper limit register_1 TDPWDMX_1 16 H FB62 TDP_1 16 2 TDP pulse width lower lim...

Page 888: ...0 TCMIER_0 8 H FBCA TCM_0 8 2 TCM cycle lower limit register_0 TCMMINCM_0 16 H FBCC TCM_0 16 2 TCM timer counter_1 TCMCNT_1 16 H FBD0 TCM_1 16 2 TCM cycle upper limit register_0 TCMMLCM_1 16 H FBD2 TC...

Page 889: ...verter 16 2 A D data register D ADDRD 16 H FC06 A D converter 16 2 A D data register E ADDRE 16 H FC08 A D converter 16 2 A D data register F ADDRF 16 H FC0A A D converter 16 2 A D data register G ADD...

Page 890: ...8 2 FSI general purpose register 2 FSIGPR2 8 H FC58 FSI 8 2 FSI general purpose register 3 FSIGPR3 8 H FC59 FSI 8 2 FSI general purpose register 4 FSIGPR4 8 H FC5A FSI 8 2 FSI general purpose registe...

Page 891: ...register 1 FSITDR1 8 H FC99 FSI 8 2 FSI transmit data register 2 FSITDR2 8 H FC9A FSI 8 2 FSI transmit data register 3 FSITDR3 8 H FC9B FSI 8 2 FSI transmit data register 4 FSITDR4 8 H FC9C FSI 8 2 F...

Page 892: ...8 2 PWM duty setting register 4_B PWMREG4_B 8 H FD18 PWMU_B 8 2 PWM prescaler register 4_B PWMPRE4_B 8 H FD19 PWMU_B 8 2 PWM duty setting register 5_B PWMREG5_B 8 H FD1A PWMU_B 8 2 PWM prescaler regi...

Page 893: ...PORT 8 2 Port 6 noise canceler decision control register P6NCMC 8 H FE01 PORTS 0 PORT 8 2 Port 6 noise cancel cycle setting register P6NCCS 8 H FE02 PORTS 0 PORT 8 2 Port C noise canceler enable regi...

Page 894: ...ta register 2 TWR2 8 H FE22 LPC 8 2 Bidirectional data register 3 TWR3 8 H FE23 LPC 8 2 Bidirectional data register 4 TWR4 8 H FE24 LPC 8 2 Bidirectional data register 5 TWR5 8 H FE25 LPC 8 2 Bidirect...

Page 895: ...C 8 2 Host interface control register 0 HICR0 8 H FE40 LPC 8 2 Host interface control register 1 HICR1 8 H FE41 LPC 8 2 Host interface control register 2 HICR2 8 H FE42 LPC 8 2 Host interface control...

Page 896: ...TCNT_0 16 H FE56 TPU_0 16 2 Timer general register A_0 TGRA_0 16 H FE58 TPU_0 16 2 Timer general register B_0 TGRB_0 16 H FE5A TPU_0 16 2 Timer general register C_0 TGRC_0 16 H FE5C TPU_0 16 2 Timer...

Page 897: ...I 2 C bus data register_2 ICDR_2 8 H FE8E IIC_2 8 2 Second slave address register_2 SARX_2 8 H FE8E IIC_2 8 2 I 2 C bus mode register_2 ICMR_2 8 H FE8F IIC_2 8 2 Slave address register_2 SAR_2 8 H FE8...

Page 898: ...4 PS2_2 8 2 Keyboard data buffer transmit data register_2 KBTR_2 8 H FEC5 PS2_2 8 2 Timer XY control register TCRXY 8 H FEC6 TMR_XY 8 2 Timer control register_Y TCR_Y 8 H FEC8 RELOCATE 1 TMR_Y 8 2 Tim...

Page 899: ...BRR_1 8 H FF89 SCI_1 8 2 I 2 C bus status register_1 ICSR_1 8 H FF89 RELOCATE 0 IIC_1 8 2 Serial control register_1 SCR_1 8 H FF8A SCI_1 8 2 Transmit data register_1 TDR_1 8 H FF8B SCI_1 8 2 Serial st...

Page 900: ...ter_0 TCSR_0 8 H FFA8 Write WDT_0 16 2 Timer control status register_0 TCSR_0 8 H FFA8 Read WDT_0 8 2 Timer counter _0 TCNT_0 8 H FFA8 Write WDT_0 16 2 Timer counter _0 TCNT_0 8 H FFA9 Read WDT_0 8 2...

Page 901: ...BB PORTS 0 PORT 8 2 Port B output data register PBODR 8 H FFBC PORTS 0 PORT 8 2 Port 8 data direction register P8DDR 8 H FFBD Write PORTS 0 PORT 8 2 Port B input data register PBPIN 8 H FFBD Read PORT...

Page 902: ...ister_0 ICDR_0 8 H FFDE IIC_0 8 2 Second slave address register_0 SARX_0 8 H FFDE IIC_0 8 2 I 2 C bus mode register_0 ICMR_0 8 H FFDF IIC_0 8 2 Slave address register_0 SAR_0 8 H FFDF IIC_0 8 2 Keyboa...

Page 903: ...3 TMR_X 8 2 Time constant register B_Y TCORB_Y 8 H FFF3 RELOCATE 0 TMR_Y 8 2 Keyboard matrix interrupt register A KMIMRA 8 H FFF3 RELOCATE 0 INT 8 2 Timer counter _X TCNT_X 8 H FFF4 TMR_X 8 2 Timer co...

Page 904: ...PJ5NOCR PJ4NOCR PJ3NOCR PJ2NOCR PJ1NOCR PJ0NOCR PORT CCR1 CIRE SRES CPHS MLS REPRCVE CLK1 CLK0 CCR2 TFM1 TFM0 CSTR CIRBUSY CIRRDRF REPF OVRF REND ABF FRF HEADF CEIR REPIE OVEIE RENDIE ABIE FREIE HEADF...

Page 905: ...it 2 bit 1 bit 0 TDPCSR_0 OVF TWDMXOVF TWDMNUDF TPDMXOVF ICPF CMF CKSEG TPDMNUDF TDPCR1_0 CST POCTL CPSPE IEDG TDPMDS CKS2 CKS1 CKS0 TDPIER_0 OVIE TWDMXIE TWDMNIE TPDMXIE ICPIE CMIE TDPIPE TPDMNIE TDP...

Page 906: ...9 bit 8 TDPWDMX_2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 TDPICR_2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 15 bit 14 bit 13 bi...

Page 907: ...7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 TCMCSR_1 OVF MAXOVF CMF CKSEG ICPF MINUDF MCICTL TCMCR_1 CST POCTL CPSPE IEDG TCMMDS CKS2 CKS1 CKS0 TCMIER_1 OVIE MAXOVIE CMIE TCMIPE ICPIE MINUDIE CMMS bit...

Page 908: ...M_3 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 TCM_3 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ADDRA bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11...

Page 909: ...1 CKSEL0 SCIFRST REGRST SCIF FSIHBARH bit31 bit30 bit29 bit28 bit27 bit26 bit25 bit24 FSIHBARL bit23 bit22 bit21 bit20 bit19 bit18 bit17 bit16 FSISR FSIMS1 FSIMS0 CMDHBARH bit31 bit30 bit29 bit28 bit2...

Page 910: ...19 bit18 bit17 bit16 FSIWDRLH bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 FSIWDRLL bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 FSICR1 SRES FSIE FRDE AAIE CPHS CPOS CKSEL FSICR2 TE RE FSITEIE FSIRXIE FSI...

Page 911: ...CLK1 CLK0 PWMCONB_A PWM5E PWM4E PWM3E PWM2E PWM1E PWM0E PWMCONC_A CNTMD01 PWMSL5 PWMSL4 PWMSL3 PWMSL2 PWMSL1 PWMSL0 PWMCOND_A PH5S PH4S PH3S PH2S PH1S PH0S CNTMD45 CNTMD23 PWMU_A PWMREG0_B bit 7 bit...

Page 912: ...2 bit 11 bit 10 bit 9 bit 8 LADR2L bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SCIFADRH bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 SCIFADRL bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit...

Page 913: ...6NOCR PD5NOCR PD4NOCR PD3NOCR PD2NOCR PD1NOCR PD0NOCR PORT TWR0MW bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 TWR0SW bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 TWR1 bit 7 bit 6 bit 5 bit 4 bi...

Page 914: ...R2 DBU27 DBU26 DBU25 DBU24 C D2 DBU22 IBF2 OBF2 HISEL SELSTR3 SELIRQ11 SELIRQ10 SELIRQ9 SELIRQ6 SELSMI SELIRQ12 SELIRQ1 HICR0 LPC3E LPC2E LPC1E FGA20E SDWNE PMEE LSMIE LSCIE HICR1 LPCBSY CLKREQ IRQBSY...

Page 915: ...t 12 bit 11 bit 10 bit 9 bit 8 TGRB_0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 TGRC_0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 1...

Page 916: ...BBSY IRIC SCP ICSR_2 ESTP STOP IRTR AASX AL AAS ADZ ACKB ICRES_2 CLR3 CLR2 CLR1 CLR0 ICXR_2 STOPIM HNDS ICDRF ICDRE ALIE ALSL FNC1 FNC0 SARX_2 SVAX6 SVAX5 SVAX4 SVAX3 SVAX2 SVAX1 SVAX0 FSX ICDR_2 ICD...

Page 917: ...it 0 TCNT_Y bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 TMR_Y ICDR_1 ICDR7 ICDR6 ICDR5 ICDR4 ICDR3 ICDR2 ICDR1 ICDR0 SARX_1 SVAX6 SVAX5 SVAX4 SVAX3 SVAX2 SVAX1 SVAX0 FSX ICMR_1 MLS WAIT CKS2 CKS1...

Page 918: ...A ABRKCR CMF BIE BARA A23 A22 A21 A20 A19 A18 A17 A16 BARB A15 A14 A13 A12 A11 A10 A9 A8 BARC A7 A6 A5 A4 A3 A2 A1 IER16 IRQ15E IRQ14E IRQ13E IRQ12E IRQ11E IRQ10E IRQ9E IRQ8E ISR16 IRQ15F IRQ14F IRQ13...

Page 919: ...WDT_0 PAODR PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR PAPIN PA7PIN PA6PIN PA5PIN PA4PIN PA3PIN PA2PIN PA1PIN PA0PIN PADDR PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR P1PCR P...

Page 920: ...INTM0 XRST NMIEG KINWUE RAME MDCR EXPE MDS2 MDS1 MDS0 SYSTEM BCR ICIS0 BRSTRM BRSTS1 BRSTS0 IOS1 IOS0 WSCR ABW AST WMS1 WMS0 WC1 WC0 BSC TCR_0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 TCR_1 CMIEB C...

Page 921: ...1 TCR_X CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 TCSR_X CMFB CMFA OVF ICF OS3 OS2 OS1 OS0 TICRR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 TICRF bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0...

Page 922: ...nitialized PORT PJDDR Initialized PIODR Initialized PJODR Initialized PIPIN PJPIN PJPCR Initialized PINOCR Initialized PJNOCR Initialized CCR1 Initialized CIR CCR2 Initialized CSTR Initialized CEIR In...

Page 923: ...alized TDPCSR_0 Initialized TDPCR1_0 Initialized TDPIER_0 Initialized TDPCR2_0 Initialized TDPWDMN_0 Initialized TDPCNT_1 Initialized TDP_1 TDPPDMX_1 Initialized TDPPDMN_1 Initialized TDPWDMX_1 Initia...

Page 924: ...MMLCM_0 Initialized TCMICR_0 Initialized TCMICRF_0 Initialized TCMCSR_0 Initialized TCMCR_0 Initialized TCMIER_0 Initialized TCMMINCM_0 Initialized TCMCNT_1 Initialized TCM_1 TCMMLCM_1 Initialized TCM...

Page 925: ...tialized A D converter ADDRC Initialized Initialized Initialized Initialized ADDRD Initialized Initialized Initialized Initialized ADDRE Initialized Initialized Initialized Initialized ADDRF Initializ...

Page 926: ...ized FSICMDR Initialized FSILSTR1 Initialized FSILSTR2 Initialized FSIGPR1 Initialized FSIGPR2 Initialized FSIGPR3 Initialized FSIGPR4 Initialized FSIGPR5 Initialized FSIGPR6 Initialized FSIGPR7 Initi...

Page 927: ...FSIRDR Initialized PWMREG0_A Initialized Initialized Initialized Initialized PWMU_A PWMPRE0_A Initialized Initialized Initialized Initialized PWMREG1_A Initialized Initialized Initialized Initialized...

Page 928: ...zed PWMREG2_B Initialized Initialized Initialized Initialized PWMPRE2_B Initialized Initialized Initialized Initialized PWMREG3_B Initialized Initialized Initialized Initialized PWMPRE3_B Initialized...

Page 929: ...lized SCIFADRL Initialized LADR4H Initialized LADR4L Initialized IDR4 Initialized ODR4 Initialized STR4 Initialized HICR4 Initialized SIRQCR2 Initialized SIRQCR3 Initialized P6NCE Initialized PORT P6N...

Page 930: ...OCR Initialized TWR0MW Initialized LPC TWR0SW Initialized TWR1 Initialized TWR2 Initialized TWR3 Initialized TWR4 Initialized TWR5 Initialized TWR6 Initialized TWR7 Initialized TWR8 Initialized TWR9 I...

Page 931: ...IDR2 Initialized ODR2 Initialized STR2 Initialized HISEL Initialized HICR0 Initialized HICR1 Initialized HICR2 HICR3 WUEMR Initialized INT PGODR Initialized PORT PGPIN PGDDR Initialized PFODR Initiali...

Page 932: ..._2 TMDR_2 Initialized TIOR_2 Initialized TIER_2 Initialized TSR_2 Initialized TCNT_2 Initialized TGRA_2 Initialized TGRB_2 Initialized SYSCR3 Initialized SYSTEM MSTPCRA Initialized MSTPCRB Initialized...

Page 933: ...nitialized Initialized Initialized Initialized FCCS Initialized ROM FPCS Initialized FECS Initialized FKEY Initialized FMATS Initialized FTDAR Initialized TSTR Initialized TSYR Initialized TPU common...

Page 934: ...d PS2_0 KBCRL_0 Initialized KBBR_0 Initialized KBCR2_0 Initialized KBCRH_1 Initialized PS2_1 KBCRL_1 Initialized KBBR_1 Initialized KBCR2_1 Initialized KBCRH_2 Initialized PS2_2 KBCRL_2 Initialized KB...

Page 935: ...ed SCR_1 Initialized TDR_1 Initialized Initialized Initialized Initialized SSR_1 Initialized Initialized Initialized Initialized RDR_1 Initialized Initialized Initialized Initialized SCMR_1 Initialize...

Page 936: ...3DDR Initialized P4DDR Initialized P3DR Initialized P4DR Initialized P5DDR Initialized P6DDR Initialized P5DR Initialized P6DR Initialized PBODR Initialized PBPIN P8DDR Initialized P7PIN PBDDR Initial...

Page 937: ...T_0 Initialized TCNT_1 Initialized ICCR_0 Initialized IIC_0 ICSR_0 Initialized ICDR_0 SARX_0 Initialized ICMR_0 Initialized SAR_0 Initialized KBCRH_3 Initialized PS2_3 KBCRL_3 Initialized KBBR_3 Initi...

Page 938: ...1 PORT H F901 P2DDR H F902 P1DR H F903 P2DR H F904 P1PIN Read H F905 P2PIN Read H F907 P2PCR H F910 P3DDR H F911 P4DDR H F912 P3DR H F913 P4DR H F914 P3PIN Read H F915 P4PIN Read H F916 P3PCR H F920...

Page 939: ...PADDR H F951 PBDDR H F952 PAODR H F953 PBODR H F954 PAPIN Read H F955 PBPIN Read H F957 PBPCR H F960 PCDDR H F961 PDDDR H F962 PCODR H F963 PDODR H F964 PCPIN Read H F965 PDPIN Read H F966 PCPCR H F96...

Page 940: ...987 PHPCR H F988 PGNOCR H F989 PHNOCR H F98A PGNCE H F98C PGNCMC H F98E PGNCCS H F990 PIDDR No condition H F991 PJDDR H F992 PIODR H F993 PJODR H F994 PIPIN Read H F995 PJPIN Read H F996 PIPCR H F997...

Page 941: ...DMX_0 H FB44 TDPWDMN_0 H FB46 TDPPDMX_0 H FB48 TDPICR_0 H FB4A TDPICRF_0 H FB4C TDPCSR_0 H FB4D TDPCR1_0 H FB4E TDPIER_0 H FB4F TDPCR2_0 H FB50 TDPPDMN_0 H FB60 TDPCNT_1 MSTPA5 0 TDP_1 H FB62 TDPWDMX_...

Page 942: ...PDMN_1 H FBC0 TCMCNT_0 MSTPB1 0 TCM_0 H FBC2 TCMMLCM_0 H FBC4 TCMICR_0 H FBC6 TCMICRF_0 H FBC8 TCMCSR_0 H FBC9 TCMCR_0 H FBCA TCMIER_0 H FBCC TCMMINCM_0 H FBD0 TCMCNT_1 MSTPB1 0 TCM_1 H FBD2 TCMMLCM_1...

Page 943: ...MICR_3 H FBF6 TCMICRF_3 H FBF8 TCMCSR_3 H FBF9 TCMCR_3 H FBFA TCMIER_3 H FBFC TCMMINCM_3 H FC00 ADDRA MSTP9 0 A D converter H FC02 ADDRB H FC04 ADDRC H FC06 ADDRD H FC08 ADDRE H FC0A ADDRF H FC0C ADDR...

Page 944: ...FC53 CMDHBARH H FC54 CMDHBARL H FC55 FSICMDR H FC56 FSILSTR1 H FC57 FSIGPR1 H FC58 FSIGPR2 H FC59 FSIGPR3 H FC5A FSIGPR4 H FC5B FSIGPR5 H FC5C FSIGPR6 H FC5D FSIGPR7 H FC5E FSIGPR8 H FC5F FSIGPR9 H F...

Page 945: ...FC95 FSIPPINS H FC96 FSISTR H FC98 FSITDR0 H FC99 FSITDR1 H FC9A FSITDR2 H FC9B FSITDR3 H FC9C FSITDR4 H FC9D FSITDR5 H FC9E FSITDR6 H FC9F FSITDR7 H FCA0 FSIRDR H FD00 PWMREG0_A MSTPB0 0 PWMU_A H FD0...

Page 946: ...D12 PWMREG1_B H FD13 PWMPRE1_B H FD14 PWMREG2_B H FD15 PWMPRE2_B H FD16 PWMREG3_B H FD17 PWMPRE3_B H FD18 PWMREG4_B H FD19 PWMPRE4_B H FD1A PWMREG5_B H FD1B PWMPRE5_B H FD1C PWMCONA_B H FD1D PWMCONB_B...

Page 947: ...PC H FDC1 LADR1L H FDC2 LADR2H H FDC3 LADR2L H FDC4 SCIFADRH H FDC5 SCIFADRL H FDD4 LADR4H H FDD5 LADR4L H FDD6 IDR4 H FDD7 ODR4 H FDD8 STR4 H FDD9 HICR4 H FDDA SIRQCR2 H FDDB SIRQCR3 H FE00 P6NCE POR...

Page 948: ...No condition PORT H FE11 PTCNT1 H FE12 PTCNT2 H FE14 P9PCR PORTS 0 H FE16 PGNOCR H FE19 PFNOCR H FE1C PCNOCR H FE1D PDNOCR H FE20 TWR0MW MSTP0 0 LPC TWR0SW H FE21 TWR1 H FE22 TWR2 H FE23 TWR3 H FE24...

Page 949: ...H FE36 SIRQCR0 H FE37 SIRQCR1 H FE38 IDR1 H FE39 ODR1 H FE3A STR1 H FE3B SIRQCR4 H FE3C IDR2 H FE3D ODR2 H FE3E STR2 H FE3F HISEL H FE40 HICR0 H FE41 HICR1 H FE42 HICR2 H FE43 HICR3 H FE45 WUEMR No co...

Page 950: ...ORL_0 H FE54 TIER_0 H FE55 TSR_0 H FE56 TCNT_0 H FE58 TGRA_0 H FE5A TGRB_0 H FE5C TGRC_0 H FE5E TGRD_0 H FE70 TCR_2 TPU_2 H FE71 TMDR_2 H FE72 TIOR_2 H FE74 TIER_2 H FE75 TSR_2 H FE76 TCNT_2 H FE78 TG...

Page 951: ...FE8E SARX_2 ICE in ICCR_2 0 H FE8F ICMR_2 ICE in ICCR_2 1 H FE8F SAR_2 ICE in ICCR_2 0 H FEA0 DACR RELOCATE 1 MSTP11 0 MSTPA1 0 REGS in DACNT DADRB 1 PWMX DADRAH RELOCATE 1 H FEA1 DADRAL RELOCATE 1 H...

Page 952: ...R_0 H FEC2 KBCR1_1 H FEC3 KBTR_1 H FEC4 KBCR1_2 H FEC5 KBTR_2 H FEC6 TCRXY MSTP8 0 TMR_XY H FEC8 TCR_Y RELOCATE 1 TMR_Y H FEC9 TCSR_Y RELOCATE 1 H FECA TCORA_Y RELOCATE 1 H FECB TCORB_Y RELOCATE 1 H F...

Page 953: ...TP3 0 IIC_1 H FED8 KBCRH_0 MSTP2 0 PS2 H FED9 KBCRL_0 H FEDA KBBR_0 H FEDB KBCR2_0 H FEDC KBCRH_1 H FEDD KBCRL_1 H FEDE KBBR_1 H FEDF KBCR2_1 H FEE0 KBCRH_2 H FEE1 KBCRL_2 H FEE2 KBBR_2 H FEE3 KBCR2_2...

Page 954: ...FF84 SBYCR RELOCATE 1 No condition LPWRCR RELOCATE 0 FLSHE in STCR 0 H FF85 LPWRCR RELOCATE 1 No condition MSTPCRH RELOCATE 0 FLSHE in STCR 0 H FF86 MSTPCRH RELOCATE 1 No condition MSTPCRL RELOCATE 0...

Page 955: ...CE in STCR 1 ICE in ICCR_1 0 H FF8F ICMR_1 RELOCATE 0 ICE in ICCR_1 1 SAR_1 RELOCATE 0 ICE in ICCR_1 0 H FFA0 DADRAH RELOCATE 0 REGS in DACNT DADRB 0 PWMX DACR RELOCATE 0 MSTP11 0 MSTPA1 0 IICE in STC...

Page 956: ...WMX DACNTL RELOCATE 0 MSTP11 0 MSTPA1 0 IICE in STCR 1 REGS in DACNT DADRB 1 H FFA8 TCSR_0 No condition WDT_0 TCNT_0 Write H FFA9 TCNT_0 Read H FFAA PAODR PORTS 0 PORT H FFAB PAPIN Read PADDR Write H...

Page 957: ...FC4 SYSCR H FFC5 MDCR H FFC6 BCR No condition BSC H FFC7 WSCR H FFC8 TCR_0 MSTP12 0 TMR_0 TMR_1 H FFC9 TCR_1 H FFCA TCSR_0 H FFCB TCSR_1 MSTP12 0 TMR_0 TMR_1 H FFCC TCORA_0 H FFCD TCORA_1 H FFCE TCORB...

Page 958: ...OCATE 1 MSTP8 0 TMR_X TCR_X RELOCATE 0 TMRX Y in TCONRS 0 TCR_Y RELOCATE 0 MSTP8 0 KINWUE in SYSCR 0 TMRX Y in TCONRS 1 TMR_Y H FFF1 KMIMR RELOCATE 0 MSTP2 0 KINWUE in SYSCR 1 INT TCSR_X RELOCATE 1 MS...

Page 959: ...TCNT_X RELOCATE 0 TMRX Y in TCONRS 0 TCNT_Y RELOCATE 0 MSTP8 0 KINWUE in SYSCR 0 TMRX Y in TCONRS 1 TMR_Y H FFF5 TCORC RELOCATE 1 MSTP8 0 TMR_X TCORC RELOCATE 0 MSTP8 0 KINWUE in SYSCR 0 TMRX Y in TCO...

Page 960: ...E84 8 2 INT WUESR 8 H FE85 8 2 INT WER 8 H FE86 8 2 INT ICRD 8 H FE87 8 2 INT ICRA 8 H FEE8 8 2 INT ICRB 8 H FEE9 8 2 INT ICRC 8 H FEEA 8 2 INT ISR 8 H FEEB 8 2 INT ISCRH 8 H FEEC 8 2 INT ISCRL 8 H FE...

Page 961: ...F902 PORTS 1 8 2 PORT P2DR 8 H F903 PORTS 1 8 2 PORT P1PIN 8 H F904 Read PORTS 1 8 2 PORT P2PIN 8 H F905 Read PORTS 1 8 2 PORT P1PCR 8 H F906 PORTS 1 8 2 PORT P2PCR 8 H F907 PORTS 1 8 2 PORT P3DDR 8...

Page 962: ...Read PORTS 1 8 2 PORT P6NCE 8 H F92B PORTS 1 8 2 PORT P6NCMC 8 H F92D PORTS 1 8 2 PORT P6NCCS 8 H F92F PORTS 1 8 2 PORT P8DDR 8 H F931 PORTS 1 8 2 PORT P8DR 8 H F933 PORTS 1 8 2 PORT P7PIN 8 H F934 R...

Page 963: ...H F957 PORTS 1 8 2 PORT PCDDR 8 H F960 PORTS 1 8 2 PORT PDDDR 8 H F961 PORTS 1 8 2 PORT PCODR 8 H F962 PORTS 1 8 2 PORT PDODR 8 H F963 PORTS 1 8 2 PORT PCPIN 8 H F964 Read PORTS 1 8 2 PORT PDPIN 8 H...

Page 964: ...ORTS 1 8 2 PORT PFNOCR 8 H F979 PORTS 1 8 2 PORT PGDDR 8 H F980 PORTS 1 8 2 PORT PHDDR 8 H F981 PORTS 1 8 2 PORT PGODR 8 H F982 PORTS 1 8 2 PORT PHODR 8 H F983 PORTS 1 8 2 PORT PGPIN 8 H F984 Read POR...

Page 965: ...8 2 PORT PINOCR 8 H F998 8 2 PORT PJNOCR 8 H F999 8 2 PORT P6NCE 8 H FE00 PORTS 0 8 2 PORT P6NCMC 8 H FE01 PORTS 0 8 2 PORT P6NCCS 8 H FE02 PORTS 0 8 2 PORT PCNCE 8 H FE03 PORTS 0 8 2 PORT PCNCMC 8 H...

Page 966: ...12 PORTS 0 8 2 PORT P9PCR 8 H FE14 PORTS 0 8 2 PORT PGNOCR 8 H FE16 PORTS 0 8 2 PORT PFNOCR 8 H FE19 PORTS 0 8 2 PORT PCNOCR 8 H FE1C PORTS 0 8 2 PORT PDNOCR 8 H FE1D PORTS 0 8 2 PORT PGODR 8 H FE46 P...

Page 967: ...8 2 PORT PCDDR 8 H FE4E Write PORTS 0 8 2 PORT PDPIN 8 H FE4F Read PORTS 0 8 2 PORT PDDDR 8 H FE4F Write PORTS 0 8 2 PORT KMPCR 8 H FE82 RELOCATE 1 PORTS 0 8 2 PORT PAODR 8 H FFAA PORTS 0 8 2 PORT PA...

Page 968: ...0 8 2 PORT P4DR 8 H FFB7 PORTS 0 8 2 PORT P5DDR 8 H FFB8 PORTS 0 8 2 PORT P6DDR 8 H FFB9 PORTS 0 8 2 PORT P5DR 8 H FFBA PORTS 0 8 2 PORT P6DR 8 H FFBB PORTS 0 8 2 PORT PBODR 8 H FFBC PORTS 0 8 2 PORT...

Page 969: ...H FB4F 8 2 TDP_0 TDPPDMN_0 16 H FB50 16 2 TDP_1 TDPCNT_1 16 H FB60 16 2 TDP_1 TDPWDMX_1 16 H FB62 6 2 TDP_1 TDPWDMN_1 16 H FB64 16 2 TDP_1 TDPPDMX_1 16 H FB66 16 2 TDP_1 TDPICR_1 16 H FB68 16 2 TDP_1...

Page 970: ..._0 16 H FBCC 16 2 TCM_1 TCMCNT_1 16 H FBD0 16 2 TCM_1 TCMMLCM_1 16 H FBD2 16 2 TCM_1 TCMICR_1 16 H FBD4 16 2 TCM_1 TCMICRF_1 16 H FBD6 16 2 TCM_1 TCMCSR_1 8 H FBD8 8 2 TCM_1 TCMCR_1 8 H FBD9 8 2 TCM_1...

Page 971: ...2 FSI FSICMDR 8 H FC55 8 2 FSI FSILSTR1 8 H FC56 8 2 FSI FSIGPR1 8 H FC57 8 2 FSI FSIGPR2 8 H FC58 8 2 FSI FSIGPR3 8 H FC59 8 2 FSI FSIGPR4 8 H FC5A 8 2 FSI FSIGPR5 8 H FC5B 8 2 FSI FSIGPR6 8 H FC5C...

Page 972: ...8 2 FSI FSIPPINS 8 H FC95 8 2 FSI FSISTR 8 H FC96 8 2 FSI FSITDR0 8 H FC98 8 2 FSI FSITDR1 8 H FC99 8 2 FSI FSITDR2 8 H FC9A 8 2 FSI FSITDR3 8 H FC9B 8 2 FSI FSITDR4 8 H FC9C 8 2 FSI FSITDR5 8 H FC9D...

Page 973: ...8 2 PWMU_A PWMREG3 8 H FD06 8 2 PWMU_A PWMPRE3 8 H FD07 8 2 PWMU_A PWMREG4 8 H FD08 8 2 PWMU_A PWMPRE4 8 H FD09 8 2 PWMU_A PWMREG5 8 H FD0A 8 2 PWMU_A PWMPRE5 8 H FD0B 8 2 PWMU_A PWMCONA 8 H FD0C 8 2...

Page 974: ...FEA0 RELOCATE 1 8 2 PWMX DADRAL 8 H FEA1 RELOCATE 1 8 2 PWMX DADRBH 8 H FEA6 RELOCATE 1 8 2 PWMX DACNTH 8 H FEA6 RELOCATE 1 8 2 PWMX DADRBL 8 H FEA7 RELOCATE 1 8 2 PWMX DACNTL 8 H FEA7 RELOCATE 1 8 2...

Page 975: ...0 TGRD_0 16 H FE5E 16 2 TPU_1 TCR_1 8 H FD40 8 2 TPU_1 TMDR_1 8 H FD41 8 2 TPU_1 TIOR_1 8 H FD42 8 2 TPU_1 TIER_1 8 H FD44 8 2 TPU_1 TSR_1 8 H FD45 8 2 TPU_1 TCNT_1 16 H FD46 16 2 TPU_1 TGRA_1 16 H FD...

Page 976: ...CR_X 8 H FFF0 8 2 TMR_X TCSR_X 8 H FFF1 8 2 TMR_X TICRR 8 H FFF2 8 2 TMR_X TICRF 8 H FFF3 8 2 TMR_X TCNT_X 8 H FFF4 8 2 TMR_X TCORC 8 H FFF5 8 2 TMR_X TCORA_X 8 H FFF6 8 2 TMR_X TCORB_X 8 H FFF7 8 2 T...

Page 977: ...8 H FFA9 Read 8 2 WDT_1 TCSR_1 8 H FFEA Write 16 2 WDT_1 TCSR_1 8 H FFEA Read 8 2 WDT_1 TCNT_1 8 H FFEA Write 16 2 WDT_1 TCNT_1 8 H FFEB Read 8 2 SCI_1 SMR_1 8 H FF88 8 2 SCI_1 BRR_1 8 H FF89 8 2 SCI_...

Page 978: ...ECF RELOCATE 1 8 2 IIC_1 SAR_1 8 H FECF RELOCATE 1 8 2 IIC_1 ICCR_1 8 H FED0 RELOCATE 1 8 2 IIC_1 ICSR_1 8 H FED1 RELOCATE 1 8 2 IIC_1 ICXR_1 8 H FED5 8 2 IIC_1 ICCR_1 8 H FF88 RELOCATE 0 8 2 IIC_1 IC...

Page 979: ...8 H FEDB 8 2 PS2_1 KBCR1_1 8 H FEC2 8 2 PS2_1 KBTR_1 8 H FEC3 8 2 PS2_1 KBCRH_1 8 H FEDC 8 2 PS2_1 KBCRL_1 8 H FEDD 8 2 PS2_1 KBBR_1 8 H FEDE 8 2 PS2_1 KBCR2_1 8 H FEDF 8 2 PS2_2 KBCR1_2 8 H FEC4 8 2...

Page 980: ...4 8 H FDD9 8 2 LPC SIRQCR2 8 H FDDA 8 2 LPC SIRQCR3 8 H FDDB 8 2 LPC TWR0MW 8 H FE20 8 2 LPC TWR0SW 8 H FE20 8 2 LPC TWR1 8 H FE21 8 2 LPC TWR2 8 H FE22 8 2 LPC TWR3 8 H FE23 8 2 LPC TWR4 8 H FE24 8 2...

Page 981: ...FE3E 8 2 LPC HISEL 8 H FE3F 8 2 LPC HICR0 8 H FE40 8 2 LPC HICR1 8 H FE41 8 2 LPC HICR2 8 H FE42 8 2 LPC HICR3 8 H FE43 8 2 A D converter ADDRA 16 H FC00 16 2 A D converter ADDRB 16 H FC02 16 2 A D c...

Page 982: ...8 H FC26 8 2 SCIF FSCR 8 H FC27 8 2 SCIF SCIFCR 8 H FC28 8 2 ROM FCCS 8 H FEA8 8 2 ROM FPCS 8 H FEA9 8 2 ROM FECS 8 H FEAA 8 2 ROM FKEY 8 H FEAC 8 2 ROM FMATS 8 H FEAD 8 2 ROM FTDAR 8 H FEAE 8 2 SYST...

Page 983: ...elected for port D Vin 0 3 to VCC 0 3 Input voltage AN input is selected for port D Vin 0 3 to VCC 0 3 or 0 3 to AVCC 0 3 whichever is lower Input voltage port 7 Vin 0 3 to AVCC 0 3 Reference power su...

Page 984: ...N7 to KIN0 KIN15 to KIN8 WUE15 to WUE8 VT VCC 0 7 ExIRQ7 to ExIRQ6 and ExIRQ15 to ExIRQ8 VT VT VCC 0 05 RES NMI MD2 MD1 and ETRST 2 VIH VCC 0 9 VCC 0 3 Input high voltage EXTAL VCC 0 7 VCC 0 3 Port 7...

Page 985: ...0 Vin 0 5 to VCC 0 5 V Input pull up MOS current Ports 1 to 3 P95 to P90 ports 6 B to D F H and J Ip 20 150 A Vin 0 V All pins Cin 10 pF Vin 0 V Input capacitance f 1 MHz Ta 25 C Supply current 4 Norm...

Page 986: ...97 P86 P52 and P42 ICE bit in ICCR is 0 high levels are driven by NMOS An external pull up resistor is necessary to provide high level output from these pins when they are used as an output 3 Indicate...

Page 987: ...VCC 3 0 V to 3 6 V VSS 0V Item Symbol Min Typ Max Unit Permissible output low current per pin SCL0 SDA0 SCL1 SDA1 SCL2 SDA2 ExSCLA ExSDAA ExSCLB ExSDAB PS2AC to PS2DC PS2AD to S2DD and PA7 to PA4 bus...

Page 988: ...T VT VCC 0 05 Input high voltage VIH VCC 0 7 5 5 Input low voltage VIL 0 5 VCC 0 3 VOL 0 5 IOL 8 mA Output low voltage 0 4 IOL 3 mA Input capacitance Cin 10 pF Vin 0 V f 1 MHz Ta 25 C Three state leak...

Page 989: ...rts 1 to 3 C and D LED 600 Figure 28 2 LED Drive Circuit Example 28 3 AC Characteristics Figure 28 3 shows the test conditions for the AC characteristics 3 V RL RH C LSI output pin C 30pF All ports RL...

Page 990: ...ing Condition A VCC 3 0 V to 3 6 V VSS 0 V 8 MHz to 10 MHz Condition B VCC 3 0 V to 3 6 V VSS 0 V 10 MHz to 20 MHz Condition A Condition B Item Symbol Min Max Min Max Unit Reference Clock cycle time t...

Page 991: ...2008 Page 965 of 994 REJ09B0452 0100 tOSC1 EXTAL VCC RES tDEXT Figure 28 5 Oscillation Stabilization Timing KINi i 0 to 15 WUEi i 8 to 15 PS2AC to PS2DC tOSC2 NMI IRQi i 0 to 15 Figure 28 6 Oscillati...

Page 992: ...0 V 32 768 kHz 8 MHz to maximum operating frequency Item Symbol Min Max Unit Test Conditions RES setup time tRESS 200 ns RES pulse width tRESW 20 tcyc Figure 28 7 NMI setup time tNMIS 150 NMI hold ti...

Page 993: ...tics Rev 1 00 Apr 28 2008 Page 967 of 994 REJ09B0452 0100 tIRQS IRQ Edge input tIRQH tNMIS tNMIH tIRQS IRQ Level input NMI IRQi i 0 to 15 tNMIW tIRQW tIRQS tIRQH KINi i 0 to 15 WUEi i 0 to 15 tIRQW Fi...

Page 994: ...I O ports Input data hold time tPRH 30 ns Figure 28 9 Timer output delay time tTOCD 50 Timer input setup time tTICS 30 Figure 28 10 Timer clock input setup time tTCKS 30 ns Single edge tTCKWH 1 5 TPU...

Page 995: ...re 28 21 FSI Clock cycle tCYC 30 ns Figure 28 22 Clock pulse width high tCKH 13 Clock pulse width low tCKL 13 SS signal rise delay time tSSH 12 SS signal fall delay time tSSL 12 Transmit signal delay...

Page 996: ...TIOCD0 Output compare outputs Input capture inputs tTOCD tTICS Figure 28 10 TPU Input Output Timing TCLKA to TCLKD tTCKWL tTCKWH tTCKS tTCKS Figure 28 11 TPU Clock Input Timing tTMOD TMO_0 TMO_1 TMO_...

Page 997: ...994 REJ09B0452 0100 tTMRS TMI_0 TMI_1 TMI_X TMI_Y Figure 28 14 8 Bit Timer Reset Input Timing tTCMS TCMCYI TCMMCI Figure 28 15 TCM Input Setup Time tTCMCKS TCMCKI tTCMCKW tTCMCKW Figure 28 16 TCM Clo...

Page 998: ...tTDPCKW Figure 28 18 TDP Clock Input Timing PWMU5A to PWMU0A PWMU5B to PWMU0B PWX1 PWX0 tPWOD Figure 28 19 PWMU PWMX Output Timing tScyc tSCKr tSCKW SCK1 tSCKf Figure 28 20 SCK Clock Input Timing SCK...

Page 999: ...C 3 0 V to 3 6 V VSS 0 V 8 MHz to maximum operating frequency Standard Value Item Symbol Min Typ Max Unit Test Conditions Remarks KCLK KD output fall time tKBF 250 ns KCLK KD input data hold time tKBI...

Page 1000: ...al Characteristics Rev 1 00 Apr 28 2008 Page 974 of 994 REJ09B0452 0100 1 Receive KCLK KD KCLK KD tKBIS tKBIH Transmit b tKBF 2 Transmit a KCLK KD tKBOD Note KCLK PS2AC to PS2DC KD PS2AD to PS2DD Figu...

Page 1001: ...bus free time tBUF 5 Start condition input hold time tSTAH 3 Retransmission start condition input setup time tSTAS 3 Stop condition input setup time tSTOS 3 Data input setup time tSDAS 0 5 tcyc Data...

Page 1002: ...cle tLcyc 30 Input clock pulse width H tLCKH 11 Input clock pulse width L tLCKL 11 Transmit signal delay time tTXD 2 11 Transmit signal floating delay time tOFF 28 Receive signal setup time tRXS 7 Rec...

Page 1003: ...t Test Conditions ETCK clock cycle time tTCKcyc 50 125 ETCK clock high pulse width tTCKH 20 ETCK clock low pulse width tTCKL 20 ETCK clock rise time tTCKr 5 ETCK clock fall time tTCKf 5 ns Figure 28 2...

Page 1004: ...2008 Page 978 of 994 REJ09B0452 0100 ETCK tTCKH tTCKf tTCKcyc tTCKL tTCKr Figure 28 27 JTAG ETCK Timing ETRST ETCK tTRSTW RES tRSTHW Figure 28 28 Reset Hold Timing tTMSS tTMSH tTDIS tTDIH tTDOD ETDO...

Page 1005: ...3 0 V to 3 6 V AVref 3 0 V to AVCC VSS AVSS 0 V 8 MHz to 20 MHz Condition Item Min Typ Max Unit Resolution 10 Bits Conversion time 4 0 s Analog input capacitance 20 pF Permissible signal source imped...

Page 1006: ...tE 600 1500 ms 64 Kbyte block Programming time total 1 2 4 tP 1 4 4 s 160 Kbytes Ta 25 C Erase time total 1 2 4 tE 1 4 4 s 160 Kbytes Ta 25 C Programming and Erase time total 1 2 4 tPE 2 9 8 s 160 Kby...

Page 1007: ...in Always connect a capacitor for internal step down power stabilization Use one or two ceramic multilayer capacitor s 0 1 F 0 47 F connect in parallel when using two and place it them near the pin It...

Page 1008: ...Section 28 Electrical Characteristics Rev 1 00 Apr 28 2008 Page 982 of 994 REJ09B0452 0100...

Page 1009: ...I O port Port 97 T keep keep keep I O port Port 96 EXCL T DDR 1 H DDR 0 T EXCL input keep DDR 1 Clock output DDR 0 T Clock output EXCL input Input port Ports 95 to 90 T keep keep keep I O port Ports A...

Page 1010: ...e 984 of 994 REJ09B0452 0100 B Product Lineup Product Type Type Code Mark Code Package Code F2117RTE20V PTQP0144LC A TFP 144V F2117RBG20V PLBG0176GA A BP 176V H8S 2117R Flash memory version R4F2117R F...

Page 1011: ...18 0 23 0 05 0 10 0 15 1 20 17 8 18 0 18 2 1 00 16 0 16 0 15 0 4 0 5 0 6 0 07 18 2 18 0 17 8 Reference Symbol Dimension in Millimeters Min Nom Max Previous Code JEITA Package Code RENESAS Code TFP 14...

Page 1012: ...BP 176V 0 45g D E w S A w S B x4 x b v y1 S y S S A 1 A A B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 e e Z E ZD A B C D E F G H J K L M N P R M S A B Dimension in Millimeters Min Nom Max Reference Symbol...

Page 1013: ...6 5 4 3 2 1 D E L 11 12 13 M N Z e Z e b A E D PTLG0145JB A P TFLGA145 9x9 0 65 0 15g MASS Typ Previous Code JEITA Package Code RENESAS Code e A1 Max Nom Min Dimension in Millimeters Symbol Reference...

Page 1014: ...D1 Always used as mode pins NMI Connect to VCC via a pull up resistor EXTAL Always used as a clock pin XTAL Always used as a clock pin Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 8 Port 9 Port A Po...

Page 1015: ...lock structure 753 Boot mode 750 776 Branch instructions 53 Buffer operation 275 Bus controller BSC 133 C Cascaded connection 380 Clock pulse generator 833 Clocked synchronous mode 441 CMIA 384 CMIB 3...

Page 1016: ...ion set 45 Interface 403 Internal block diagram 8 Interrupt controller 85 Interrupt exception handling 81 interrupt exception handling vector table 108 Interrupt mask bit 40 interrupt mask level 39 In...

Page 1017: ...r direct 57 Register field 56 Register indirect 57 Register indirect with displacement 58 Register indirect with post Increment 58 Register indirect with pre decrement 58 Registers ABRKCR 91 ADCR 734...

Page 1018: ...10 TCMIER 315 TCMMINCM 310 TCMMLCM 309 TCNT 263 360 394 TCONRI 373 TCONRS 373 TCOR 361 TCR 243 362 TCSR 367 TDPCNT 333 TDPCR1 338 TDPCR2 340 TDPCSR 335 TDPICR 335 TDPICRF 335 TDPIER 341 TDPPDMN 334 TD...

Page 1019: ...ation 273 System control instructions 54 T TCI0V 288 TCI1U 288 TCI1V 288 TCI2U 288 TCI2V 288 TEI1 460 TGI0A 288 TGI0B 288 TGI0C 288 TGI0D 288 TGI1A 288 TGI1B 288 TGI2A 288 TGI2B 288 Toggle output 270...

Page 1020: ...Rev 1 00 Apr 28 2008 Page 994 of 994 REJ09B0452 0100...

Page 1021: ...oup Publication Date Rev 1 00 Apr 28 2008 Published by Sales Strategic Planning Div Renesas Technology Corp Edited by Customer Support Department Global Strategic Communication Div Renesas Solutions C...

Page 1022: ...7898 Renesas Technology Hong Kong Ltd 7th Floor North Tower World Finance Centre Harbour City Canton Road Tsimshatsui Kowloon Hong Kong Tel 852 2265 6688 Fax 852 2377 3473 Renesas Technology Taiwan Co...

Page 1023: ......

Page 1024: ...H8S 2117R Group Hardware Manual...

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