Renesas H8S/2100 Series, Hardware Manual

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Section 26 Power-Down Modes
Rev. 1.00 Apr. 28, 2008 Page 851 of 994
REJ09B0452-0100
26.4 Sleep Mode
The CPU makes a transition to sleep mode if the SLEEP instruction is executed when the SSBY
bit in SBYCR is cleared to 0 and the LSON bit in LPWRCR is cleared to 0. In sleep mode, CPU
operation stops but the on-chip peripheral modules do not. The contents of the CPU’s internal
registers are retained.
Sleep mode is cleared by any interrupt or the
RES
pin input.
When an interrupt occurs, sleep mode is cleared and interrupt exception handling starts. Sleep
mode is not cleared if the interrupt is disabled, or interrupts other than NMI have been masked by
the CPU.
When the
RES
pin is driven low and sleep mode is cleared, a transition is made to the reset state.
After the specified reset input time has elapsed, driving the
RES
pin high causes the CPU to start
reset exception handling.
26.5 Software Standby Mode
The CPU makes a transition to software standby mode when the SLEEP instruction is executed
with the SSBY bit in SBYCR set to 1, the LSON bit in LPWRCR cleared to 0, and the PSS bit in
TCSR (WDT_1) cleared to 0. In software standby mode, the CPU, on-chip peripheral modules,
and clock pulse generator all stop. However, the contents of the CPU registers, on-chip RAM data,
I/O ports, and the states of on-chip peripheral modules other than the SCI, PWMU, PWMX, and
A/D converter are retained as long as the prescribed voltage is supplied.
Software standby mode is cleared by an external interrupt (NMI, IRQ0 to IRQ15, KIN0 to KIN15,
or WUE8 to WUE15), PS2 interrupt, or
RES
pin input.
When an external interrupt request signal is input, system clock oscillation starts, and after the
elapse of the time set in bits STS2 to STS0 in SBYCR, software standby mode is cleared, and
interrupt exception handling is started. When clearing software standby mode with an IRQ0 to
IRQ15 interrupt, set the corresponding enable bit to 1. When clearing software standby mode with
a KIN0 to KIN15 or WUE8 to WUE15 interrupt, enable the input. In these cases, ensure that no
interrupt with a higher priority than interrupts IRQ0 to IRQ15 is generated. In the case of an IRQ0
to IRQ15 interrupt, software standby mode is not cleared if the corresponding enable bit is cleared
to 0 or if the interrupt has been masked by the CPU. In the case of a KIN0 to KIN15 or WUE8 to
WUE15 interrupt, software standby mode is not cleared if the input is disabled or if the interrupt
has been masked by the CPU.