Renesas H8S/2100 Series, Hardware Manual

Page: 886 / 1024

Section 27 List of Registers
Rev. 1.00 Apr. 28, 2008 Page 860 of 994
REJ09B0452-0100
Register Name Abbreviation
Number
of bits
Address Module
Data
Width Access
States
Port I data direction register PIDDR 8 H'F990 PORT 8 2
Port J data direction register PJDDR 8 H'F991 PORT 8 2
Port I output data register PIODR 8 H'F992 PORT 8 2
Port J output data register PJODR 8 H'F993 PORT 8 2
Port I input data register PIPIN 8 H'F994 (Read) PORT 8 2
Port J input data register PJPIN 8 H'F995 (Read) PORT 8 2
Port J pull-up MOS control register PJPCR 8 H'F997 PORT 8 2
Port I Nch-OD control register PINOCR 8 H'F998 PORT 8 2
Port J Nch-OD control register PJNOCR 8 H'F999 PORT 8 2
Receive control register 1
CCR1 8 H'FA40 CIR 8 2
Receive control register 2 CCR2 8 H'FA41
CIR
8 2
Receive status register CSTR 8 H'FA42 CIR 8 2
Interrupt enable register CEIR 8 H'FA43
CIR
8 2
Bit rate register
BRR 8 H'FA44 CIR 8 2
Receive data register 0 to 7
CIRRDR0 to
CIRRDR7 8 H'FA45 CIR 8 2
Header minimum high-level period
register
HHMIN 16 H'FA46
CIR
8 2
Header maximum high-level period
register
HHMAX 16 H'FA48
CIR
8 2
Header minimum low-level period
register HLMIN 8 H'FA4A CIR 8 2
Header maximum low-level period
register
HLMAX 8 H'FA4B
CIR
8 2
Data level 0 minimum period register DT0MIN 8 H'FA4C CIR
8 2
Data level 0 maximum period
register
DT0MAX 8 H'FA4D
CIR
8 2
Data level 1 minimum period register DT1MIN 8 H'FA4E CIR 8 2
Data level 1 maximum period
register DT1MAX 8 H'FA4F
CIR
8 2
Repeat header minimum low-level
period register RMIN 8 H'FA50 CIR 8 2
Repeat header maximum low-level
period register
RMAX 8 H'FA51 CIR 8 2