Renesas H8S/2100 Series, Hardware Manual

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Section 21 FSI Interface
Rev. 1.00 Apr. 28, 2008 Page 694 of 994
REJ09B0452-0100
21.3.10 FSI Access Host Base Address Registers H and L (FSIHBARH and FSIHBARL)
FSIHBARH and FSIHBARL store the upper 16 bits of the host start address which is necessary to
convert the host address to the SPI flash memory address. The input range of the host address will
be determined based on the host start address set in these registers and the memory size set in
FSISR. If a host address to be input is out of the determined range, Sync will not be returned. If
FW memory cycle is used, bit 31 to bit 28 in FSIHBARH is set as IDSEL. During FSI operation
(in the state where FSIE or FSILIE is set), do not change the setting in this register.
•
FSIHBARH
R/W
Bit Bit Name
Initial
Value
EC Host Description
7 to 0 bit 31 to
bit 24
All 0 R/W

These bits specify bits [31:24] of the host start
address.
•
FSIHBARL
R/W
Bit Bit Name
Initial
Value
EC Host Description
7 to 0 bit 23 to
bit 16
All 0 R/W

These bits specify bits [23:16] of the host start
address.
The settings by bit 19 to bit 16 do not affect the
operation.
21.3.11 FSI Flash Memory Size Register (FSISR)
FSISR sets the size of SPI flash memory. The host input address range will be determined based
on the size set in this register. Note that the host input address should not be greater than the SPI
flash memory capacity. During FSI operation (in the state where FSIE or FSILIE is set), do not
change the setting in this register.