Renesas H8S/2100 Series, Hardware Manual

Page: 156 / 1024

Section 5 Interrupt Controller
Rev. 1.00 Apr. 28, 2008 Page 130 of 994
REJ09B0452-0100
5.8.2 Instructions for Disabling Interrupts
The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these
instructions are executed, all interrupts including NMI are disabled and the next instruction is
always executed. When the I bit or UI bit is set by one of these instructions, the new value
becomes valid two states after execution of the instruction ends.
5.8.3 Interrupts during Execution of EEPMOV Instruction
Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction.
With the EEPMOV.B instruction, an interrupt request including NMI issued during data transfer is
not accepted until data transfer is completed.
With the EEPMOV.W instruction, if an interrupt request is issued during data transfer, interrupt
exception handling starts at a break in the transfer cycles. The PC value saved on the stack in this
case is the address of the next instruction. Therefore, if an interrupt is generated during execution
of an EEPMOV.W instruction, the following coding should be used.
L1: EEPMOV.W
MOV.W R4,R4
BNE L1
5.8.4 Vector Address Switching
Switching between H8S/2140B Group compatible vector mode and extended vector mode must be
done in a state with no interrupts occurring.
If the EIVS bit in SYSCR3 is changed from 0 to 1 when interrupt input is enabled because the
KIN15
to
KIN0
and
WUE15
to
WUE8
pins are set at low level, a falling edge is detected, thus
causing an interrupt to be generated. The vector mode must be changed when interrupt input is
disabled, that is the
KIN15
to
KIN0
and
WUE15
to
WUE8
pins are set at high level.