Section 4 Exception Handling
Rev. 1.00 Apr. 28, 2008 Page 82 of 994
REJ09B0452-0100
4.6
Exception Handling by Illegal Instruction
The exception handling by the illegal instruction starts when an undefined code is executed. The
exception handling by the illegal instruction is always executable in the program execution state.
The exception handling operates as follows:
1. The contents of the PC and CCR are saved in the stack.
2. The interrupt mask bit is updated.
3. An exception handling vector table address corresponding to the occurred exception is
generated, the start address of the exception service routine is loaded from the vector table to
the PC, and program execution starts from that address.
Table 4.5 shows the state of CCR after execution of illegal instruction exception handling.
Table 4.5
Status of CCR after Illegal Instruction Exception Handling
CCR
Interrupt Control Mode
I
UI
0
Set to 1
Retains the previous value
1
Set to 1
Set to 1
Illegal instruction code is not detected for fields that do not affect the definition of the instruction,
such as an effective address extension (EA) and register fields. In addition, the instruction code of
instructions consisting of multiple words are detected individually and are not detected as
combinations of instruction codes.
Do not execute instruction codes that are not defined. The contents of general registers are not
guaranteed after the execution of an undefined instruction code or exception handling by the
illegal instruction. The value of the stack pointer at the time of exception handling by the illegal
instruction and the saved contents of the PC are also not guaranteed.
Summary of Contents for H8S/2100 Series
Page 2: ...Rev 1 00 Apr 28 2008 Page ii of xxvi...
Page 54: ...Section 1 Overview Rev 1 00 Apr 28 2008 Page 28 of 994 REJ09B0452 0100...
Page 92: ...Section 2 CPU Rev 1 00 Apr 28 2008 Page 66 of 994 REJ09B0452 0100...
Page 158: ...Section 5 Interrupt Controller Rev 1 00 Apr 28 2008 Page 132 of 994 REJ09B0452 0100...
Page 244: ...Section 8 8 Bit PWM Timer PWMU Rev 1 00 Apr 28 2008 Page 218 of 994 REJ09B0452 0100...
Page 330: ...Section 10 16 Bit Timer Pulse Unit TPU Rev 1 00 Apr 28 2008 Page 304 of 994 REJ09B0452 0100...
Page 416: ...Section 13 8 Bit Timer TMR Rev 1 00 Apr 28 2008 Page 390 of 994 REJ09B0452 0100...
Page 612: ...Section 18 I 2 C Bus Interface IIC Rev 1 00 Apr 28 2008 Page 586 of 994 REJ09B0452 0100...
Page 706: ...Section 20 LPC Interface LPC Rev 1 00 Apr 28 2008 Page 680 of 994 REJ09B0452 0100...
Page 752: ...Section 21 FSI Interface Rev 1 00 Apr 28 2008 Page 726 of 994 REJ09B0452 0100...
Page 774: ...Section 23 RAM Rev 1 00 Apr 28 2008 Page 748 of 994 REJ09B0452 0100...
Page 1008: ...Section 28 Electrical Characteristics Rev 1 00 Apr 28 2008 Page 982 of 994 REJ09B0452 0100...
Page 1020: ...Rev 1 00 Apr 28 2008 Page 994 of 994 REJ09B0452 0100...
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