Renesas H8S/2100 Series, Hardware Manual

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Section 13 8-Bit Timer (TMR)
Rev. 1.00 Apr. 28, 2008 Page 381 of 994
REJ09B0452-0100
13.7 TMR_Y and TMR_X Cascaded Connection
If bits CKS2 to CKS0 in either TCR_Y or TCR_X are set to B'100, the 8-bit timers of the two
channels are cascaded. With this configuration, 16-bit count mode or compare-match count mode
can be selected by the settings of the CKSX and CKSY bits in TCRXY.
13.7.1 16-Bit Count Mode
When bits CKS2 to CKS0 in TCR_Y are set to B'100 and the CKSY bit in TCRXY is set to 1, the
timer functions as a single 16-bit timer with TMR_Y occupying the upper eight bits and TMR_X
occupying the lower 8 bits.
•
Setting of compare-match flags

The CMF flag in TCSR_Y is set to 1 when an upper 8-bit compare-match occurs.

The CMF flag in TCSR_X is set to 1 when a lower 8-bit compare-match occurs.
•
Counter clear specification

If the CCLR1 and CCLR0 bits in TCR_Y have been set for counter clear at compare-
match, only the upper eight bits of TCNT_Y are cleared. The upper eight bits of TCNT_Y
are also cleared when counter clear by the TMRIY pin has been set.

The settings of the CCLR1 and CCLR0 bits in TCR_X are enabled, and the lower 8 bits of
TCNT_X can be cleared by the counter.
•
Pin output

Control of output from the TMOY pin by bits OS3 to OS0 in TCSR_Y is in accordance
with the upper 8-bit compare-match conditions.

Control of output from the TMOX pin by bits OS3 to OS0 in TCSR_X is in accordance
with the lower 8-bit compare-match conditions.
13.7.2 Compare-Match Count Mode
When bits CKS2 to CKS0 in TCR_X are set to B'100 and the CKSX bit in TCRXY is set to 1,
TCNT_X counts the occurrence of compare-match A for TMR_Y. TMR_X and TMR_Y are
controlled independently. Conditions such as setting of the CMF flag, generation of interrupts,
output from the TMO pin, and counter clearing are in accordance with the settings for each
channel.