Renesas H8S/2100 Series, Hardware Manual

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Section 7 I/O Ports
Rev. 1.00 Apr. 28, 2008 Page 145 of 994
REJ09B0452-0100
7.1.2 Data Register (PnDR) (n = 1 to 6, 8, and 9)
DR is a register that stores output data of the pins to be used as the general output port. Since the
P96DR bit is determined by the state of the P96 pin, the initial value is undefined. The upper five
bits in P5DR and the upper one bit in P8DR are reserved.
Bit Bit Name Initial Value R/W Description
7 Pn7DR 0 R/W
6 Pn6DR 0 R/W
5 Pn5DR 0 R/W
4 Pn4DR 0 R/W
3 Pn3DR 0 R/W
2 Pn2DR 0 R/W
1 Pn1DR 0 R/W
0 Pn0DR 0 R/W
PnDR stores output data for the pins that are used
as the general output port.
When the PORTS bit in PTCNT2 is 0, reading this
register reads out the current settings of these bits
for pins corresponding to PnDDR bits set to 1 and
reads out the states of pins corresponding to
PnDDR bits cleared to 0.
7.1.3 Input Data Register (PnPIN) (n = 1 to 9 and A to J)
PIN is an 8-bit read-only register that reflects the port pin state. A write to PIN is invalid. The
upper five bits in P5PIN, the upper one bit in P8PIN, the upper three bits in PEPIN, and the upper
two bits in PHPIN are reserved.
Bits P1PIN to P9PIN are valid only when PORTS in PTCNT2 is 1.
Bit Bit Name Initial Value R/W Description
7 Pn7PIN Undefined
*
R
6 Pn6PIN Undefined
*
R
5 Pn5PIN Undefined
*
R
4 Pn4PIN Undefined
*
R
3 Pn3PIN Undefined
*
R
2 Pn2PIN Undefined
*
R
1 Pn1PIN Undefined
*
R
0 Pn0PIN Undefined
*
R
When this register is read, the pin states are
returned.
Note: * The initial values of these pins are determined in accordance with the states of pins Pn7
to Pn0.