Section 19
Keyboard Buffer Control Unit (PS2)
Rev. 1.00 Apr. 28, 2008 Page 601 of 994
REJ09B0452-0100
19.4.2 Transmit
Operation
In a transmit operation, KCLK (clock) is an output on the keyboard side, and KD (data) is an
output on the chip (system) side. KD outputs a start bit, 8 data bits (LSB-first), an odd parity bit,
and a stop bit, in that order. The KD value is valid when KCLK is high. A sample transmit
processing flowchart is shown in figure 19.5, and the transmit timing in figure 19.6.
KDO retains 1
[4]
[3]
[2]
[1]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
Set KBIOE bit
Write 1 to the KBIOE bit to enable transmission/
reception.
Clear the KBE bit (reception disabled).
Write transmit data to KBTR.
Read KBCRH, and when both the KCLKI and
KDI bits are 1, write 0 to the KCLKO bit to set
the I/O inhibit. 60
µ
s or more is required for I/O
inhibit.
Read KBCRH, and when the KDI bit is 1, write
0 to the KDO (set start bit).
Write 1 to the KBTS bit to enter the transmit
enabled state.
Write 1 to the KCLKO bit to clear the I/O inhibit.
Check D0 to D7, the parity bit, the stop bit, and
receive completion notification (send data at the
falling edge of the KCLK signal).
The KBTE bit is set to 1 at the eleventh rising
edge of the KCLK signal. When KTIE = 1, a
CPU interrupt occurs.
When KTER = 0, transmission is successfully completed.
Clear the KBTE bit to 0.
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
Write transmit data
to KBTR
Clear KBE bit
(reception disabled)
Read KBCRH
No
Yes
No
No
No
Yes
Yes
Yes
To transmit operation or receive operation
Read KBCRH
KCLKO retains 0
KDO retains 0
Clear I/O inhibit
(KCLKO = 1)
Autmatic transmission
Clear KBTE bit
Error handling
Set KBTS
(KBTS = 1)
KBTE = 1
KTER = 0
Set start bit
(KDO = 0)
*
KDI = 1?
Receive termination
processing execution
Retransmit request
processing execution
Both KCLKI and
KDI = 1?
Set I/O inhibit
(KCLKO = 0)
Start
(Condition: KBE = 0)
Note:
*
The start bit (KDO = 0) is automatically initialized (KDO = 1)
when automatic transmission is started. After initialization,
to write 0 to KDO, read 1 before writing 0 to it.
Figure 19.5 Sample Transmit Processing Flowchart
Summary of Contents for H8S/2100 Series
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Page 54: ...Section 1 Overview Rev 1 00 Apr 28 2008 Page 28 of 994 REJ09B0452 0100...
Page 92: ...Section 2 CPU Rev 1 00 Apr 28 2008 Page 66 of 994 REJ09B0452 0100...
Page 158: ...Section 5 Interrupt Controller Rev 1 00 Apr 28 2008 Page 132 of 994 REJ09B0452 0100...
Page 244: ...Section 8 8 Bit PWM Timer PWMU Rev 1 00 Apr 28 2008 Page 218 of 994 REJ09B0452 0100...
Page 330: ...Section 10 16 Bit Timer Pulse Unit TPU Rev 1 00 Apr 28 2008 Page 304 of 994 REJ09B0452 0100...
Page 416: ...Section 13 8 Bit Timer TMR Rev 1 00 Apr 28 2008 Page 390 of 994 REJ09B0452 0100...
Page 612: ...Section 18 I 2 C Bus Interface IIC Rev 1 00 Apr 28 2008 Page 586 of 994 REJ09B0452 0100...
Page 706: ...Section 20 LPC Interface LPC Rev 1 00 Apr 28 2008 Page 680 of 994 REJ09B0452 0100...
Page 752: ...Section 21 FSI Interface Rev 1 00 Apr 28 2008 Page 726 of 994 REJ09B0452 0100...
Page 774: ...Section 23 RAM Rev 1 00 Apr 28 2008 Page 748 of 994 REJ09B0452 0100...
Page 1008: ...Section 28 Electrical Characteristics Rev 1 00 Apr 28 2008 Page 982 of 994 REJ09B0452 0100...
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