Renesas H8S/2100 Series, Hardware Manual

Page: 733 / 1024

Section 21 FSI Interface
Rev. 1.00 Apr. 28, 2008 Page 707 of 994
REJ09B0452-0100
21.4.4 FSI Memory Cycle (Direct Transfer between LPC and SPI)
The FSI supports direct transfer between the host and SPI flash memory. If the host address input
in LPC/FW memory write cycle matches the host address set in FSIHBARH, FSIHBARL, or
FSISR, the FSI memory cycle starts. In LPC/FW memory write cycle, the FSI supports three types
of instructions: Byte/Page-Program instructions and AAI-Program instruction. In LPC/FW
memory read cycle, the FSI supports two types of instructions: Read instruction and Fast-Read
instruction. In the case that LPC-SPI direct transfer is selected in Byte-Program, Page-Program, or
AAI-Program instruction execution, set FLDCT of SLCR to 1. The FSI reads the data with LPC-
SPI direct transfer regardless of the status of FLDCT in Read and Fast-Read instruction execution.
(1)
FSI Address Conversion
The host address can be converted into the SPI flash memory address by setting FSIHBARH,
FSIHBARL, and FSISR. The host address space ranges from H'0000_0000 to H'FFFF_FFFF. The
SPI flash memory address space ranges from H'00_0000 to H'FF_FFFF. Figure 21.3 shows an
example of the FSI memory address conversion.
1MB
SPI addresses
SPI flash memory
Host addresses
H'00_0000
H'0F_FFFF
FSIHBAR: H'231F
FSISR: H'00 (1 MB)
H'231F_0000
*
H'232E_FFFF
1 MB
1 MB
Note: * The upper 16 bits of the host address are set to the value in the FSIHBAR register.
Figure 21.3 FSI Address Conversion Example
As shown in figure 21.3, if an address ranging from H'231F_0000 to H'232E_FFFF is accessed in
LPC/FW memory write cycle, the SPI flash memory is accessed. If a host address to be input is
out of the determined range, Sync will not be returned. During an SPI flash memory access, a long
wait cycle will be inserted to the LPC bus cycle. In an LPC memory cycle, one-byte transfer is
enabled. In an FW memory cycle, a byte, word, and a longword transfer are enabled.