Renesas H8S/2100 Series, Hardware Manual

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Section 10 16-Bit Timer Pulse Unit (TPU)
Rev. 1.00 Apr. 28, 2008 Page 295 of 994
REJ09B0452-0100
(3) TCFV Flag/TCFU Flag Setting Timing
Figure 10.40 shows the timing for setting of the TCFV flag in TSR by overflow occurrence, and
TCIV interrupt request signal timing. Figure 10.41 shows the timing for setting of the TCFU flag
in TSR by underflow occurrence, and TCIU interrupt request signal timing.
Overflow
signal
TCNT
(overflow)
TCNT input
clock
H'FFFF H'0000
TCFV flag
TCIV interrupt
φ
Figure 10.40 TCIV Interrupt Setting Timing
Underflow
signal
TCNT
(underflow)
TCNT
input clock
H'0000 H'FFFF
TCFU flag
TCIU interrupt
φ
Figure 10.41 TCIU Interrupt Setting Timing