Renesas H8S/2100 Series, Hardware Manual

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Section 9 14-Bit PWM Timer (PWMX)
Rev. 1.00 Apr. 28, 2008 Page 233 of 994
REJ09B0452-0100
t
f1
t
f2
t
f255
t
f256
t
H1
t
H2
t
H3
t
H255
t
H256
1 conversion cycle
t
f1
= t
f2
= t
f3
= ··· = t
f255
= t
f256
= T
×
64
t
H1
+ t
H2
+ t
H3
+ ··· + t
H255
+ t
H256
= T
H
t
f1
t
f2
t
f63
t
f64
t
H1
t
H2
t
H3
t
H63
t
H64
1 conversion cycle
t
f1
= t
f2
= t
f3
= ··· = t
f63
= t
f64
= T
×
256
t
H1
+ t
H2
+ t
H3
+ ··· + t
H63
+ t
H64
= T
H
(a) CFS = 0 [base cycle = resolution (T)
×
64]
(b) CFS = 1 [base cycle = resolution (T)
×
256]
Figure 9.5 Output Waveform (OS = 1, DADR corresponds to T
H
)
An example of the additional pulses when CFS = 1 (base cycle = resolution (T)
×
256) and OS = 1
(inverted PWM output) is described below. When CFS = 1, the upper eight bits (DA13 to DA6) in
DADR determine the duty cycle of the base pulse while the subsequent six bits (DA5 to DA0)
determine the locations of the additional pulses as shown in figure 9.6.
Table 9.6 lists the locations of the additional pulses.
DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 CFS
1 1
Duty cycle of base pulse Location of additional pulses
Figure 9.6 D/A Data Register Configuration when CFS = 1