Renesas H8S/2100 Series, Hardware Manual

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Section 10 16-Bit Timer Pulse Unit (TPU)
Rev. 1.00 Apr. 28, 2008 Page 275 of 994
REJ09B0452-0100
10.5.3 Buffer Operation
Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer
registers. Buffer operation differs depending on whether TGR has been designated as an input
capture register or as a compare match register. Table 10.18 shows the register combinations used
in buffer operation.
Table 10.18 Register Combinations in Buffer Operation
Channel Timer General Register Buffer Register
0 TGRA_0 TGRC_0
TGRB_0 TGRD_0
•
When TGR is an output compare register
When a compare match occurs, the value in the buffer register for the corresponding channel is
transferred to the timer general register. This operation is illustrated in figure 10.16.
Buffer register
Timer general
register
TCNT Comparator
Compare match signal
Figure 10.16 Compare Match Buffer Operation
•
When TGR is an input capture register
When input capture occurs, the value in TCNT is transferred to TGR and the value previously
held in the timer general register is transferred to the buffer register. This operation is
illustrated in figure 10.17.
Buffer register
Timer general
register
TCNT
Input capture
signal
Figure 10.17 Input Capture Buffer Operation