Renesas H8S/2100 Series, Hardware Manual

Page: 757 / 1024

Section 22 A/D Converter
Rev. 1.00 Apr. 28, 2008 Page 731 of 994
REJ09B0452-0100
22.3.1 A/D Data Registers A to H (ADDRA to ADDRH)
There are eight 16-bit read-only ADDR registers, ADDRA to ADDRH, used to store the results of
A/D conversion. The ADDR registers which store a conversion result for each channel are shown
in table 22.3.
The 10-bit conversion data is stored in bits 15 to 6. The lower six bits are always read as 0.
The data bus between the CPU and the A/D converter is sixteen bits wide. The data can be read
directly from the CPU. ADDR must not be accessed in 8-bit units and must be accessed in 16-bit
units.
Table 22.3 Analog Input Channels and Corresponding ADDR
Analog Input Channel
Channel Set 0 (CH3
=
0) Channel Set 1 (CH3
=
1)
A/D Data Register to Store A/D
Conversion Results
AN0 AN8 ADDRA
AN1 AN9 ADDRB
AN2 AN10 ADDRC
AN3 AN11 ADDRD
AN4 AN12 ADDRE
AN5 AN13 ADDRF
AN6 AN14 ADDRG
AN7 AN15 ADDRH