Renesas H8S/2100 Series, Hardware Manual

Page: 353 / 1024

Section 11 16-Bit Cycle Measurement Timer (TCM)
Rev. 1.00 Apr. 28, 2008 Page 327 of 994
REJ09B0452-0100
11.6.5 Conflict between Edge Detection in Cycle Measurement Mode and Clearing of
TCMMDS Bit in TCMCR
If the CST bit in TCMCR is set to 1 in cycle measurement mode, and the TCMMDS bit in
TCMCR is cleared, but the selected edge from TCMCYI is detected at the same time, detection of
the selected edge will cause the timer to continue to operate in cycle measurement mode. The
timer will not make the transition to timer mode until the next detection of the selected edge. Thus,
ensure that the CST bit is cleared to 0 in cycle measurement mode.
Figure 11.17 shows the timing of this conflict.
Internal write
signal
Input capture
signal
N + 1 N H'0000 M
N M L
φ
TCMCYI
TCMCNT cleared at the
first rising edge
TCMCNT not cleared
TCMCNT
TCMICR
TCMMDS
Figure 11.17 Conflict between Edge Detection and Clearing of TCMMDS
(to Switch from Cycle Measurement Mode to Timer Mode)
11.6.6 Settings of TCMCKI and TCMMCI
TCMCKI and TCMMCI are multiplexed on the same pin of this LSI. Therefore, the selected
external clock and the TCMMCI signal cannot be used at the same time. Do not make the settings
CKS2 to CKS0
=
B'111 and CMMS
=
B'1.
11.6.7 Setting for Module Stop Mode
The module-stop control register can be used to select either continuation or stoppage of TCM
operation in module-stopped mode. The default setting is for TCM operation to stop. TCM
registers become accessible on release from module stop mode. For details, see section 26, Power-
Down Modes.