Renesas H8S/2100 Series, Hardware Manual

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Section 2 CPU
Rev. 1.00 Apr. 28, 2008 Page 35 of 994
REJ09B0452-0100
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions
uses an 8-bit absolute address included in the instruction code to specify a memory operand
that contains a branch address. In advanced mode the operand is a 32-bit longword operand,
providing a 32-bit branch address. The upper 8 bits of these 32 bits is a reserved area that is
regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF.
Note that the first part of this range is also used for the exception vector table.
•
Stack Structure
In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine
call, and the PC, condition-code register (CCR), and extended control register (EXR) are
pushed onto the stack in exception handling, they are stored as shown in figure 2.4. When
EXR is not pushed onto the stack in interrupt control mode 0. For details, see section 4,
Exception Handling.
PC
(24 bits)
EXR
*
1
Reserved
*
1
,
*
3
CCR
PC
(24 bits)
SP
SP
(SP
*
2
Reserved
(a) Subroutine Branch (b) Exception Handling
Notes: 1. When EXR is not used it is not stored on the stack.
2. SP when EXR is not used.
3. Ignored when returning.
)
Figure 2.4 Stack Structure in Advanced Mode