Renesas H8S/2100 Series, Hardware Manual

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Section 5 Interrupt Controller
Rev. 1.00 Apr. 28, 2008 Page 129 of 994
REJ09B0452-0100
5.8 Usage Notes
5.8.1 Conflict between Interrupt Generation and Disabling
When an interrupt enable bit is cleared to 0 to disable interrupt requests, the disabling becomes
effective after execution of the instruction. When an interrupt enable bit is cleared to 0 by an
instruction such as BCLR or MOV, and if an interrupt is generated during execution of the
instruction, the interrupt concerned will still be enabled on completion of the instruction, so
interrupt exception handling for that interrupt will be executed on completion of the instruction.
However, if there is an interrupt request of higher priority than that interrupt, interrupt exception
handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be
ignored. The same rule is also applied when an interrupt source flag is cleared to 0. Figure 5.13
shows an example where the CMIEA bit in TCR of the TMR is cleared to 0. The above conflict
will not occur if an interrupt enable bit or interrupt source flag is cleared to 0 while the interrupt is
disabled.
Internal
address bus
Internal
write signal
φ
CMIEA
CMFA
CMIA
interrupt signal
TCR write cycle by CPU CMIA exception handling
TCR address
Figure 5.13 Conflict between Interrupt Generation and Disabling