Renesas H8S/2100 Series, Hardware Manual

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Section 14 Watchdog Timer (WDT)
Rev. 1.00 Apr. 28, 2008 Page 391 of 994
REJ09B0452-0100
Section 14 Watchdog Timer (WDT)
This LSI incorporates two watchdog timer channels (WDT_0 and WDT_1). The watchdog timer
can generate an internal reset signal or an internal NMI interrupt signal if a system crash prevents
the CPU from writing to the timer counter, thus allowing it to overflow.
When this watchdog function is not needed, the WDT can be used as an interval timer. In interval
timer operation, an interval timer interrupt is generated each time the counter overflows. A block
diagram of the WDT_0 and WDT_1 are shown in figure 14.1.
14.1 Features
•
Selectable from eight (WDT_0) or 16 (WDT_1) counter input clocks.
•
Switchable between watchdog timer mode and interval timer mode
Watchdog Timer Mode:
•
If the counter overflows, whether an internal reset or an internal NMI interrupt is generated
can be selected.
Interval Timer Mode:
•
If the counter overflows, an interval timer interrupt (WOVI) is generated.