Renesas H8S/2100 Series, Hardware Manual

Page: 767 / 1024

Section 22 A/D Converter
Rev. 1.00 Apr. 28, 2008 Page 741 of 994
REJ09B0452-0100
22.7 Usage Notes
22.7.1 Module Stop Mode Setting
The A/D converter operation can be enabled or disabled using the module stop control register.
With the initial setting, the A/D converter is stopped. Register access is enabled by canceling
module stop mode. For details, see section 26, Power-Down Modes.
22.7.2 Permissible Signal Source Impedance
This LSI’s analog input is designed so that the conversion accuracy is guaranteed for an input
signal for which the signal source impedance is 5 k
Ω
or less. This specification is provided to
enable the A/D converter’s sample-and-hold circuit input capacitance to be charged within the
sampling time; if the sensor output impedance exceeds 5 k
Ω
, charging may be insufficient and it
may not be possible to guarantee the A/D conversion accuracy. However, if a large capacitance is
provided externally in single mode, the input load will essentially comprise only the internal input
resistance of 10 k
Ω
, and the signal source impedance is ignored. However, since a low-pass filter
effect is obtained in this case, it may not be possible to follow an analog signal with a large
differential coefficient (e.g., voltage fluctuation ratio of 5 mV/µs or greater) (see figure 22.5).
When converting a high-speed analog signal or converting in scan mode, a low-impedance buffer
should be inserted.
A/D converter equivalent circuit
This LSI
20 pF
C
in
=
10 pF
10 k
Ω
Up to 5 k
Ω
Low-pass
filter C
Up to 0.1 µF
Sensor output
impedance
Sensor input
Figure 22.5 Example of Analog Input Circuit