Section 16 CIR Interface
Rev. 1.00 Apr. 28, 2008 Page 483 of 994
REJ09B0452-0100
(2)
Stop
When a low-level period of 9 ms or more is detected after the reception of a command, the CIR
stops data reception. This is not defined in the NEC format.
Command
Stop
C = 0.56 ms
D = 1.78 ms
C
A = 9.0 ms
CIRI
A: Low-level period for a stop
C: High-level period for logic 0/1, low-level period for logic 0, and high-level period for a stop
D: Low-level period for logic 1
[Legend]
Figure 16.4 Stop
(3)
Repeat
When a key of the remote controller remains pressed, the command is sent only once, followed by
a repeat signal. When a 9-ms high level and the following 2.25-ms low level are detected, they are
recognized as a repeat header.
Repeat
Repeat - Header
A = 9.0 ms
E = 2.25 ms
C = 0.56 ms
[Legend]
A: High-level period for a repeat header
E: Low-level period for a repeat header
C: High-level period for a repeat
CIRI
Figure 16.5 Repeat
Summary of Contents for H8S/2100 Series
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Page 54: ...Section 1 Overview Rev 1 00 Apr 28 2008 Page 28 of 994 REJ09B0452 0100...
Page 92: ...Section 2 CPU Rev 1 00 Apr 28 2008 Page 66 of 994 REJ09B0452 0100...
Page 158: ...Section 5 Interrupt Controller Rev 1 00 Apr 28 2008 Page 132 of 994 REJ09B0452 0100...
Page 244: ...Section 8 8 Bit PWM Timer PWMU Rev 1 00 Apr 28 2008 Page 218 of 994 REJ09B0452 0100...
Page 330: ...Section 10 16 Bit Timer Pulse Unit TPU Rev 1 00 Apr 28 2008 Page 304 of 994 REJ09B0452 0100...
Page 416: ...Section 13 8 Bit Timer TMR Rev 1 00 Apr 28 2008 Page 390 of 994 REJ09B0452 0100...
Page 612: ...Section 18 I 2 C Bus Interface IIC Rev 1 00 Apr 28 2008 Page 586 of 994 REJ09B0452 0100...
Page 706: ...Section 20 LPC Interface LPC Rev 1 00 Apr 28 2008 Page 680 of 994 REJ09B0452 0100...
Page 752: ...Section 21 FSI Interface Rev 1 00 Apr 28 2008 Page 726 of 994 REJ09B0452 0100...
Page 774: ...Section 23 RAM Rev 1 00 Apr 28 2008 Page 748 of 994 REJ09B0452 0100...
Page 1008: ...Section 28 Electrical Characteristics Rev 1 00 Apr 28 2008 Page 982 of 994 REJ09B0452 0100...
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