Renesas H8S/2100 Series, Hardware Manual

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Section 13 8-Bit Timer (TMR)
Rev. 1.00 Apr. 28, 2008 Page 356 of 994
REJ09B0452-0100
Figures 13.1 and 13.2 show block diagrams of 8-bit timers.
An input capture function is added to TMR_X.
External clock sources Internal clock sources
TMR_0
φ
/2,
φ
/8,
φ
/32,
φ
/64,
φ
/256,
φ
/1024
Clock 1
Clock 0
Compare-match A1
Compare-match A0
Clear 1
Interrupt signals
CMIA0
CMIB0
OVI0
CMIA1
CMIB1
OVI1
TMO0
TMI0 (TMRI0)
Internal bus
TCORA_0
Comparator A_0
Comparator B_0
TCORB_0
TCSR_0
TCR_0
TCORA_1
Comparator A_1
TCNT_1
Comparator B_1
TCORB_1
TCSR_1
TCR_1
TMI0 (TMCI0)
TMI1 (TMCI1)
TCNT_0
Overflow 1
Overflow 0
Compare-match B1
Compare-match B0
TMO1
TMI1 (TMRI1)
Clock selection
Control logic
Clear 0
TMR_1
φ
/2,
φ
/8,
φ
/64,
φ
/128,
φ
/1024,
φ
/2048
[Legend]
TCORA_0:
TCORB_0:
TCNT_0:
TCSR_0:
TCR_0:
Time constant register A_0
Time constant register B_0
Timer counter_0
Timer control/status register_0
Timer control register_0
TCORA_1:
TCORB_1:
TCNT_1:
TCSR_1:
TCR_1:
Time constant register A_1
Time constant register B_1
Timer counter_1
Timer control/status register_1
Timer control register_1
Figure 13.1 Block Diagram of 8-Bit Timer (TMR_0 and TMR_1)