Renesas H8S/2100 Series, Hardware Manual

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Section 5 Interrupt Controller
Rev. 1.00 Apr. 28, 2008 Page 108 of 994
REJ09B0452-0100
5.4.2 Internal Interrupt Sources
Internal interrupts issued from the on-chip peripheral modules have the following features:
•
For each on-chip peripheral module there are flags that indicate the interrupt request status,
and enable bits that individually select enabling or disabling of these interrupts. When the
enable bit for a particular interrupt source is set to 1, an interrupt request is sent to the interrupt
controller.
•
The control level for each interrupt can be set by ICR.
5.5 Interrupt Exception Handling Vector Tables
Tables 5.4 and 5.5 list interrupt exception handling sources, vector addresses, and interrupt
priorities. H8S/2140B Group compatible vector mode or extended vector mode can be selected for
the vector addresses by the EIVS bit in system control register 3 (SYSCR3).
For default priorities, the lower the vector number, the higher the priority. Modules set at the same
priority will conform to their default priorities. Priorities within a module are fixed.
An interrupt control level can be specified for a module to which an ICR bit is assigned. Interrupt
requests from modules that are set to interrupt control level 1 (priority) by the interrupt control
level and the I and UI bits in CCR are given priority and processed before interrupt requests from
modules that are set to interrupt control level 0 (no priority).
Table 5.5 Interrupt Sources, Vector Addresses, and Interrupt Priorities
(H8S/2140B Group Compatible Vector Mode)
Vector Address Origin of
Interrupt
Source
Name
Vector
Number
Advanced Mode ICR Priority
External pin NMI 7 H'00001C — High
IRQ0 16 H'000040 ICRA7
IRQ1 17 H'000044 ICRA6
IRQ2
IRQ3
18
19 H'000048
H'00004C ICRA5
IRQ4
IRQ5
20
21 H'000050
H'000054 ICRA4
IRQ6, KIN7 to KIN0
IRQ7, KIN15 to KIN8 22
23 H'000058
H'00005C ICRA3
Low