Renesas H8S/2100 Series, Hardware Manual

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Section 18 I
2
C Bus Interface (IIC)
Rev. 1.00 Apr. 28, 2008 Page 569 of 994
REJ09B0452-0100
SDA
(master output)
SDA
(slave output)
2 1 4 3 6 5 8 7
1
2 9 9
A
A
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6
IRTR
ICDRF
ICDRR
SCL
(master output)
Master transmit mode Master receive mode
Data 1
Data 1 Data 2
[1] TRS=0 clear [2] ICDR read
(Dummy read)
[1] IRIC clear
SCL is fixed low until ICDR is read SCL is fixed low until ICDR is read
[4] IRIC clear User processing
IRIC
[3]
[5] ICDR read
(Data 1)
Undefined value
Figure 18.11 Example of Operation Timing in Master Receive Mode
(MLS = WAIT = 0)
SDA
(master output)
SDA
(slave output)
2 1 4 3 6 5 8 7 9 9 7 8
A
A
Bit 7 Bit 1 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
IRIC
ICDRF
ICDRR
SCL
(master output)
Data 3
Data 2
Data 1 Data 2
Data 3
[9] IRIC clear
User processing
IRTR
[8] [3]
Bit 0
[11] Set BBSY=0 and
SCP=0
(Stop condition instruction issuance)
[4] IRIC clear [7] ICDR read
(Data 2)
[10] ICDR read
(Data 3)
[6] Set ACKB = 1
Bit 0
Stop condition generation
SCL is fixed low until ICDR is read
SCL is fixed low until
stop condition is issued
Figure 18.12 Example of Stop Condition Issuance Operation Timing
in Master Receive Mode (MLS = WAIT = 0)