Renesas H8S/2100 Series, Hardware Manual

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Section 11 16-Bit Cycle Measurement Timer (TCM)
Rev. 1.00 Apr. 28, 2008 Page 314 of 994
REJ09B0452-0100
Bit Bit Name
Initial
Value R/W Description
4 IEDG 0 R/W Input Edge Select
In timer mode, selects the falling or rising edge of the
TCMCYI input for use in input capture, in combination with
the value of the POCTL bit.
In cycle measurement mode, selects the falling or rising
edge of the TCMCYI input for use in measurement, in
combination with the value of the POCTL bit.
POCTL
=
0
0: Selects the rising edge of the TCMCYI input
1: Selects the falling edge of the TCMCYI input
POCTL
=
1
0: Selects the falling edge of the TCMCYI input
1: Selects the rising edge of the TCMCYI input
3 TCMMDS 0 R/W TCM Mode Select
Selects the TCM operating mode.
0: Timer mode
The TCM provides compare match and input capture
facilities.
1: Cycle measurement mode
Setting this bit to 1 starts counting by TCMCNT. TCMCNT
should be initialized to H'0000. Clear the CST in TCMCR
to 0 before setting to cycle measurement mode.
2
1
0
CKS2
CKS1
CKS0
0
0
0
R/W
R/W
R/W
Clock Select 2, 1, 0
Selects the clock signal for input to TCMCNT.
Note: Modify this bit when CST
=
0 and TCMMDS
=
0
000: Count
φ
/2 internal clock
001: Count
φ
/8 internal clock
010: Count
φ
/16 internal clock
011: Count
φ
/32 internal clock
100: Count
φ
/64 internal clock
101: Count
φ
/128 internal clock
110: Count
φ
/256 internal clock
111: Count external clock (select the external clock edge
with CKSEG in TCMCSR.)