Section 24 Flash Memory
Rev. 1.00 Apr. 28, 2008 Page 832 of 994
REJ09B0452-0100
12. If data other than H'FF is to be written to the key code area in programmer mode, a verification
error will occur unless a software countermeasure is taken for the PROM programmer and
version of program.
13. The programming program that includes the initialization routine and the erasing program that
includes the initialization routine are each 3 kbytes or less. Accordingly, when the CPU clock
frequency is 20 MHz, the download for each program takes approximately 200
µ
s at the
maximum.
14. A programming/erasing program for the flash memory used in a conventional F-ZTAT H8,
H8S microcomputer which does not support download of the on-chip program by setting the
SCO bit in FCCS to 1 cannot run in this LSI. Be sure to download the on-chip program to
execute programming/erasing of the flash memory in this F-ZTAT H8/H8S microcomputer.
15. Unlike a conventional F-ZTAT H8/H8S microcomputers, measures against a program crash
are not taken by WDT while programming/erasing and downloading a programming/erasing
program. When needed, measures should be taken by user. A periodic interrupt generated by
the WDT can be used as the measures, as an example. In this case, the interrupt generation
period should take into consideration time to program/erase the flash memory.
16. When downloading the programming/erasing program, do not clear the SCO bit in FCCS to 0
after immediately setting it to 1. Otherwise, download cannot be performed normally.
Immediately after executing the instruction to set the SCO bit to 1, dummy read of the FCCS
must be executed twice.
17. The contents of some registers are not saved in a programming/programming end/erasing
program. When needed, save registers in the procedure program.
Summary of Contents for H8S/2100 Series
Page 2: ...Rev 1 00 Apr 28 2008 Page ii of xxvi...
Page 54: ...Section 1 Overview Rev 1 00 Apr 28 2008 Page 28 of 994 REJ09B0452 0100...
Page 92: ...Section 2 CPU Rev 1 00 Apr 28 2008 Page 66 of 994 REJ09B0452 0100...
Page 158: ...Section 5 Interrupt Controller Rev 1 00 Apr 28 2008 Page 132 of 994 REJ09B0452 0100...
Page 244: ...Section 8 8 Bit PWM Timer PWMU Rev 1 00 Apr 28 2008 Page 218 of 994 REJ09B0452 0100...
Page 330: ...Section 10 16 Bit Timer Pulse Unit TPU Rev 1 00 Apr 28 2008 Page 304 of 994 REJ09B0452 0100...
Page 416: ...Section 13 8 Bit Timer TMR Rev 1 00 Apr 28 2008 Page 390 of 994 REJ09B0452 0100...
Page 612: ...Section 18 I 2 C Bus Interface IIC Rev 1 00 Apr 28 2008 Page 586 of 994 REJ09B0452 0100...
Page 706: ...Section 20 LPC Interface LPC Rev 1 00 Apr 28 2008 Page 680 of 994 REJ09B0452 0100...
Page 752: ...Section 21 FSI Interface Rev 1 00 Apr 28 2008 Page 726 of 994 REJ09B0452 0100...
Page 774: ...Section 23 RAM Rev 1 00 Apr 28 2008 Page 748 of 994 REJ09B0452 0100...
Page 1008: ...Section 28 Electrical Characteristics Rev 1 00 Apr 28 2008 Page 982 of 994 REJ09B0452 0100...
Page 1020: ...Rev 1 00 Apr 28 2008 Page 994 of 994 REJ09B0452 0100...
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