Renesas H8S/2100 Series, Hardware Manual

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Section 15 Serial Communication Interface (SCI)
Rev. 1.00 Apr. 28, 2008 Page 458 of 994
REJ09B0452-0100
15.7.8 Clock Output Control
Clock output can be fixed using the CKE1 and CKE0 bits in SCR when the GM bit in SMR is set
to 1. Specifically, the minimum width of a clock pulse can be specified.
Figure 15.31 shows an example of clock output fixing timing when the CKE0 bit is controlled
with GM = 1 and CKE1 = 0.
Specified pulse width
SCK
CKE0
Specified pulse width
Figure 15.31 Clock Output Fixing Timing
At power-on and transitions to/from software standby mode, use the following procedure to secure
the appropriate clock duty ratio.
(1) At Power-On
To secure the appropriate clock duty ratio simultaneously with power-on, use the following
procedure.
1. Initially, port input is enabled in the high-impedance state. To fix the potential level, use a
pull-up or pull-down resistor.
2. Fix the SCK pin to the specified output using the CKE1 bit in SCR.
3. Set SMR and SCMR to enable smart card interface mode.
4. Set the CKE0 bit in SCR to 1 to start clock output.