Renesas H8S/2100 Series, Hardware Manual

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Section 20 LPC Interface (LPC)
Rev. 1.00 Apr. 28, 2008 Page 669 of 994
REJ09B0452-0100
Table 20.7 Scope of Initialization in Each LPC interface Mode
Items Initialized
System
Reset LPC
Reset
LPC
Shutdown
LPC transfer cycle sequencer (internal state), LPCBSY and ABRT
flags Initialized Initialized Initialized
SERIRQ transfer cycle sequencer (internal state), CLKREQ and
IRQBSY flags Initialized Initialized Initialized
LPC interface flags
(IBF1, IBF2, IBF3A, IBF3B, IBF4, MWMF, C/
D
1, C/
D
2, C/
D
3, C/
D
4,
OBF1, OBF2, OBF3A, OBF3B, OBF4, SWMF, DBU), GA20 (internal
state)
Initialized Initialized Retained
Host interrupt enable bits
(IRQ1E1, IRQ12E1, SMIE2, IRQ6E2, IRQ9E2 to IRQ11E2, SMIE3B,
SMIE3A, IRQ6E3, IRQ9E3 to IRQ11E3, SELREQ, SMIE4, IRQ6E4,
IRQ9E4 to IRQ11E4, IEDIR2 to IEDIR4), Q/
C
flag
Initialized Initialized Retained
LRST flag Initialized (0) Can be
set/cleared
Can be
set/cleared
SDWN flag Initialized (0) Initialized (0) Can be
set/cleared
LRSTB bit Initialized (0) HR: 0
SR: 1
0 (can be
set)
SDWNB bit Initialized (0) Initialized (0) HS: 0
SS: 1
SDWNE bit Initialized (0) Initialized (0) HS: 1
SS: 0 or 1
LPC interface operation control bits
(LPC4E to LPC1E, FGA20E, LADR1 to LADR4, IBFIE1 to IBFIE4,
PMEE, PMEB, LSMIE, LSMIB, LSCIE, LSCIB, TWRE, SELSTR3,
SELIRQ1, SELSMI, SELIRQ3 to SELIRQ15, OBEIE, SCIFE, IDR1 to
IDR4, ODR1 to ODR4, TWR0 to TWR15, SCSIRQ0 to SCSIRQ3,
and SCIFADRH/L) Initialized Retained Retained
LRESET
signal Input Input
LPCPD
signal
Input (port
function
Input Input
LAD3 to LAD0,
LFRAME
, LCLK, SERIRQ,
CLKRUN
signals Input Hi-Z
PME
,
LSMI
, LSCI, GA20 signals (when function is selected) Output Hi-Z
PME
,
LSMI
, LSCI, GA20 signals (when function is not selected) Port function Port function
Note: System reset: Reset by
RES
pin input, or WDT overflow
LPC reset: Reset by LPC hardware reset (HR) or LPC software reset (SR)
LPC shutdown: Reset by LPC hardware shutdown (HS) or LPC software shutdown (SS)