Renesas H8S/2100 Series, Hardware Manual

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Section 16 CIR Interface
Rev. 1.00 Apr. 28, 2008 Page 477 of 994
REJ09B0452-0100
16.3.5 Bit Rate Register (BRR)
BRR is an 8-bit register that adjusts the sampling clock signal used for CIR reception. The bit rate
for the CIR reception is determined by a combination of the setting value in BRR and the CLK1
and CLK0 bits in CCR1.
Bit Bit Name
Initial
Value R/W Description
7 to 0 BRR7 to
BRR1 All 1 R/W Sets the value of the sampling clock.
The following formula is used for calculating the bit rate, and the following table shows BRR
setting examples to obtain a target bit rate.
B = T / (N + 1)
B: Bit rate (bits/s)
T: Frequency of the reference clock (Hz) set by the CLK1 and CLK0 bits in CCR1 (
φ
,
φ
/2,
φ
/4, or
φ
sub)
N: Set value in BRR (0
≤
N
≤
255)
Table 16.3 Setting Example of BRR
Carrier
Frequency
φ
CLK1 and
CLK0 Setting BRR Setting
Value Bit Rate
(Kbit/s)
Deviation from
Target Carrier
Frequency
20 MHz
φ
H'FF 78.1 51.36%
φ
/2 H'FF 39.1 2.72%
38kHz
φ
/4 H'83 37.9
−
0.32%
10 MHz
φ
H'FF 39.1 2.72%
φ
/2 H'83 37.9
−
0.32%
φ
/4 H'41 37.9
−
0.32%
8 MHz
φ
H'D2 37.9
−
0.23%
φ
/2 H'69 37.7
−
0.70%
φ
/4 H'34 37.7
−
0.70%
 φ
sub H'00 32.8 2.34%