Renesas H8S/2100 Series, Hardware Manual

Page: 606 / 1024

Section 18 I
2
C Bus Interface (IIC)
Rev. 1.00 Apr. 28, 2008 Page 580 of 994
REJ09B0452-0100
The following items are not initialized:
•
Actual register values (ICDR, SAR, SARX, ICMR, ICCR, ICSR, ICXR (except for the ICDRE
and ICDRF flags)
•
Internal latches used to retain register read information for setting/clearing flags in ICMR,
ICCR, and ICSR
•
The value of the ICMR bit counter (BC2 to BC0)
•
Generated interrupt sources (interrupt sources transferred to the interrupt controller)
(2) Notes on Initialization
•
Interrupt flags and interrupt sources are not cleared, and so flag clearing measures must be
taken as necessary.
•
Basically, other register flags are not cleared either, and so flag clearing measures must be
taken as necessary.
•
When initialization is executed by ICRES, the write data for bits CLR3 to CLR0 is not
retained. To perform IIC clearance, bits CLR3 to CLR0 must be written to simultaneously
using an MOV instruction. Do not use a bit manipulation instruction such as BCLR.
•
Similarly, when clearing is required again, all the bits must be written to simultaneously in
accordance with the setting.
•
If a flag clearing setting is made during transmission/reception, the IIC module will stop
transmitting/receiving at that point and the SCL and SDA pins will be released. When
transmission/reception is started again, register initialization, etc., must be carried out as
necessary to enable correct communication as a system.
The value of the BBSY bit cannot be modified directly by this module clear function, but since the
stop condition pin waveform is generated according to the state and release timing of the SCL and
SDA pins, the BBSY bit may be cleared as a result. Similarly, state switching of other bits and
flags may also have an effect.
To prevent problems caused by these factors, the following procedure should be used when
initializing the IIC state.
1. Execute initialization of the internal state according to the setting of bits CLR3 to CLR0 or
ICE bit clearing.
2. Execute a stop condition issuance instruction (write 0 to BBSY and SCP) to clear the BBSY
bit to 0, and wait for two transfer rate clock cycles.
3. Re-execute initialization of the internal state according to the setting of bits CLR3 to CLR0 or
ICE bit clearing.
4. Initialize (re-set) the IIC registers.