Renesas H8S/2100 Series, Hardware Manual

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Section 18 I
2
C Bus Interface (IIC)
Rev. 1.00 Apr. 28, 2008 Page 562 of 994
REJ09B0452-0100
18.4.2 Initialization
Initialize the IIC by the procedure shown in figure 18.6 before starting transmission/reception of
data.
Start initialization
Set MSTP4 = 0 (IIC_0)
MSTP3 = 0 (IIC_1)
MSTPB4 = 0 (IIC_2)
(MSTPCRL, MSTPCRB)
Set ICE = 0 in ICCR
Set ICSR
Set STCR
Cancel module stop mode
Set the first and second slave addresses and IIC communication format
(SVA6 to SVA0, FS, SVAX6 to SVAX0, and FSX)
Enable ICMR and ICDR to be accessed
Use SCL/SDA pin as an IIC port
Set transfer rate (IICX)
Enable the CPU accessing to the IIC control register and data register
Set communication format, wait insertion, and transfer rate
(MLS, WAIT, CKS2 to CKS0)
Enable interrupt, set communication operation
(STOPIM, HNDS, ALIE, ALSL, FNC1, and FNC0)
Be sure to set as follows: HNDS = 1, FNC1 = 1, and FNC0 = 1.
Set acknowledge bit (ACKB)
Set ICMR
Set ICCR
Set IICE = 1 in STCR
Set SAR and SARX
Set ICE = 1 in ICCR
Set ICXR
<< Start transmit/receive operation >>
Set interrupt enable, transfer mode, and acknowledge decision
(IEIC, MST, TRS, and ACKE)
Enable SAR and SARX to be accessed
Figure 18.6 Sample Flowchart for IIC Initialization
Note: Be sure to modify the ICMR register after transmit/receive operation has been completed.
If the ICMR register is modified during transmit/receive operation, bit counter BC2 to
BC0 will be modified erroneously, thus causing incorrect operation.
18.4.3 Master Transmit Operation
In I
2
C bus format master transmit mode, the master device outputs the transmit clock and transmit
data, and the slave device returns an acknowledge signal.
Figure 18.7 shows the sample flowchart for the operations in master transmit mode.