Renesas H8S/2100 Series, Hardware Manual

Page: 685 / 1024

Section 20 LPC Interface (LPC)
Rev. 1.00 Apr. 28, 2008 Page 659 of 994
REJ09B0452-0100
20.3.19 Host Interface Select Register (HISEL)
HISEL selects the function of bits 7 to 4 in STR3 and selects the output of the host interrupt
request signal of each frame.
R/W
Bit Bit Name
Initial
Value
Slave Host Description
7 SELSTR3 0 R/W

Status Register 3 Selection
Selects the function of bits 7 to 4 in STR3 in
combination with the TWRE bit in LADR3L. For
details of STR3, see section 20.3.12, Status
Registers 1 to 4 (STR1 to STR4).
0: Bits 7 to 4 in STR3 indicate processing status of
the LPC interface.
1: [When TWRE = 1]
Bits 7 to 4 in STR3 indicate processing status of
the LPC interface.
[When TWRE = 0]
Bits 7 to 4 in STR3 are readable/writable bits
which user can use as necessary
6
5
4
3
2
1
0
SELIRQ11
SELIRQ10
SELIRQ9
SELIRQ6
SELSMI
SELIRQ12
SELIRQ1
0
0
0
0
0
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W







Host IRQ Interrupt Select
These bits select the state of the output on the
SERIRQ pins.
0: [When host interrupt request is cleared]
SERIRQ pin output is in the Hi-Z state
[When host interrupt request is set]
SERIRQ pin output is low
1: [When host interrupt request is cleared]
SERIRQ pin output is low
[When host interrupt request is set]
SERIRQ pin output is in the Hi-Z state.