Renesas H8S/2100 Series, Hardware Manual

Page: 249 / 1024

Section 9 14-Bit PWM Timer (PWMX)
Rev. 1.00 Apr. 28, 2008 Page 223 of 994
REJ09B0452-0100
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DADRB
Bit Bit Name
Initial
Value R/W Description
15
14
13
12
11
10
9
8
7
6
5
4
3
2
DA13
DA12
DA11
DA10
DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
D/A Data 13 to 0
These bits set a digital value to be converted to an
analog value.
In each base cycle, the DACNT value is continually
compared with the DADR value to determine the duty
cycle of the output waveform, and to decide whether to
output a fine-adjustment pulse equal in width to the
resolution. To enable this operation, this register must
be set within a range that depends on the CFS bit. If
the DADR value is outside this range, the PWM output
is held constant.
A channel can be operated with 12-bit precision by
fixing DA0 and DA1 to 0. The two data bits are not
compared with DACNT12 and DACNT13 of DACNT.
1 CFS 1 R/W Carrier Frequency Select
0: Base cycle = resolution (T)
×
64
DA13 to DA0 range = H'0100 to H'3FFF
1: Base cycle = resolution (T)
×
256
DA13 to DA0 range = H'0040 to H'3FFF
0 REGS 1 R/W Register Select
DADRA and DACR, and DADRB and DACNT, are
located at the same addresses. The REGS bit specifies
which registers can be accessed.
0: DADRA and DADRB can be accessed
1: DACR and DACNT can be accessed