Renesas H8S/2100 Series, Hardware Manual

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Section 13 8-Bit Timer (TMR)
Rev. 1.00 Apr. 28, 2008 Page 385 of 994
REJ09B0452-0100
13.9 Usage Notes
13.9.1 Conflict between TCNT Write and Counter Clear
If a counter clear signal is generated during the T
2
state of a TCNT write cycle as shown in figure
13.13, clearing takes priority and the counter write is not performed.
φ
Address TCNT address
Internal write signal
Counter clear signal
TCNT N H'00
T1 T2
TCNT write cycle by CPU
Figure 13.13 Conflict between TCNT Write and Clear
13.9.2 Conflict between TCNT Write and Count-Up
If a count-up occurs during the T
2
state of a TCNT write cycle as shown in figure 13.14, the
counter write takes priority and the counter is not incremented.
φ
Address TCNT address
Internal write signal
TCNT input clock
TCNT N M
T
1
T
2
TCNT write cycle by CPU
Counter write data
Figure 13.14 Conflict between TCNT Write and Count-Up