Renesas H8S/2100 Series, Hardware Manual

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Section 18 I
2
C Bus Interface (IIC)
Rev. 1.00 Apr. 28, 2008 Page 540 of 994
REJ09B0452-0100
18.3.4 I
2
C Bus Mode Register (ICMR)
ICMR sets the communication format and transfer rate. It can only be accessed when the ICE bit
in ICCR is set to 1.
Bit Bit Name
Initial
Value R/W Description
7 MLS 0 R/W MSB-First/LSB-First Select
0: MSB-first
1: LSB-first
Set this bit to 0 when the I
2
C bus format is used.
6 WAIT 0 R/W Wait Insertion Bit
This bit is valid only in master mode with the I
2
C bus
format.
0: Data and the acknowledge bit are transferred
consecutively with no wait inserted.
1: After the fall of the clock for the final data bit (8
th
clock), the IRIC flag is set to 1 in ICCR, and a wait
state begins (with SCL at the low level). When the
IRIC flag is cleared to 0 in ICCR, the wait ends and
the acknowledge bit is transferred.
For details, see section 18.4.7, IRIC Setting Timing and
SCL Control.
5
4
3
CKS2
CKS1
CKS0
0
0
0
R/W
R/W
R/W
Transfer Clock Select 2 to 0
These bits are used only in master mode.
These bits select the required transfer rate, together
with the IICX2 (IIC_2), IICX1 (IIC_1), and IICX0 (IIC_0)
bits in STCR. See table 18.4.