Section 24 Flash Memory
Rev. 1.00 Apr. 28, 2008 Page 790 of 994
REJ09B0452-0100
Yes
No
Start erasing
procedure program
Set FKEY to H'A5
Yes
No
Download error processing
Set the FPEFEQ
parameter
End erasing
procedure program
FPFR = 0?
Initialization error processing
Disable interrupts
and bus master operation
other than CPU
Clear FKEY to 0
Set parameters to
ER0 and ER1
(FMPAR and FMPDR)
Yes
No
Clear FKEY and erasing
error processing
*
Yes
Required
block erasing is
completed?
No
Set FKEY to H'A5
Clear FKEY to 0
1
1
Download
Initialization
Programming
Set FMATS to value other
than H'AA to select user MAT
Set SCO to 1 and
execute download
Set FMATS to H'AA to
select user boot MAT
User-boot-MAT selection state
User-MAT selection state
User-boot-MAT
selection state
MAT
switchover
MAT
switchover
DPFR
=
0?
Initialization
JSR FTDAR setting
+
32
Programming
JSR FTDAR setting
+
16
FPFR
=
0?
Select on-chip program
to be downloaded and
specify download
destination by FTDAR
Note:
*
The MAT must be switched by FMATS
to perform the erasing error processing
in the user boot MAT.
Figure 24.14 Procedure for Programming User MAT in User Boot Mode
The difference between the programming procedures in user program mode and user boot mode is
whether the MAT is switched or not as shown in figure 24.14.
In user boot mode, the user boot MAT can be seen in the flash memory space with the user MAT
hidden in the background. The user MAT and user boot MAT are switched only while the user
MAT is being programmed. Because the user boot MAT is hidden while the user MAT is being
programmed, the procedure program must be executed in an area other than flash memory. After
the programming procedure completes, switch the MATs again to return to the first state.
Summary of Contents for H8S/2100 Series
Page 2: ...Rev 1 00 Apr 28 2008 Page ii of xxvi...
Page 54: ...Section 1 Overview Rev 1 00 Apr 28 2008 Page 28 of 994 REJ09B0452 0100...
Page 92: ...Section 2 CPU Rev 1 00 Apr 28 2008 Page 66 of 994 REJ09B0452 0100...
Page 158: ...Section 5 Interrupt Controller Rev 1 00 Apr 28 2008 Page 132 of 994 REJ09B0452 0100...
Page 244: ...Section 8 8 Bit PWM Timer PWMU Rev 1 00 Apr 28 2008 Page 218 of 994 REJ09B0452 0100...
Page 330: ...Section 10 16 Bit Timer Pulse Unit TPU Rev 1 00 Apr 28 2008 Page 304 of 994 REJ09B0452 0100...
Page 416: ...Section 13 8 Bit Timer TMR Rev 1 00 Apr 28 2008 Page 390 of 994 REJ09B0452 0100...
Page 612: ...Section 18 I 2 C Bus Interface IIC Rev 1 00 Apr 28 2008 Page 586 of 994 REJ09B0452 0100...
Page 706: ...Section 20 LPC Interface LPC Rev 1 00 Apr 28 2008 Page 680 of 994 REJ09B0452 0100...
Page 752: ...Section 21 FSI Interface Rev 1 00 Apr 28 2008 Page 726 of 994 REJ09B0452 0100...
Page 774: ...Section 23 RAM Rev 1 00 Apr 28 2008 Page 748 of 994 REJ09B0452 0100...
Page 1008: ...Section 28 Electrical Characteristics Rev 1 00 Apr 28 2008 Page 982 of 994 REJ09B0452 0100...
Page 1020: ...Rev 1 00 Apr 28 2008 Page 994 of 994 REJ09B0452 0100...
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Page 1024: ...H8S 2117R Group Hardware Manual...